Operation process of non-volatile memory element

Abstract

The persent invention discloses an operation process of non-volatile memory element. During programming n-type channel non-volatile memory with FN tunneling effect, the control grid is applied with one positive voltage and the drain is applied with one negative volgage, the source is made floated and the substrate is applied with one negative voltage, the source is made floated and the substrate is applied with one negative voltage. During erasing n-type channel non-volatile memory with FN tunneling effect, the control grid is applied with one negative voltage and the drain is applied with one positive voltage, the source is made floated and the substrate is applied with one positive voltage.

Description

technical field [0001] The present invention relates to an operating method of a non-volatile memory (Non-Volatile Memory, NVM) element, and in particular to an operating method of an n-channel (n-Channel) non-volatile memory. Background technique [0002] Stacked Gate Memory has the advantage of being able to store, read, and erase data multiple times, and the stored data will not disappear after power off, so it has become a personal A non-volatile memory element widely used in computers and electronic equipment. [0003] A typical stacked gate storage device is made of doped polysilicon to make a floating gate (Floating Gate) and a control gate (Control Gate). When programming or erasing the stacked gate memory element, an appropriate voltage is applied to the source region, the drain region and the control gate respectively, so that electrons are injected into the polysilicon floating gate, or Electrons are pulled from the polysilicon floatin...

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Problems solved by technology

However, when the voltage used increases, the reliability of electronic components is often reduced, and it will limit the extent of component size reduction

[0013] Moreover, by figure 1 with the bias settings of Table 1 (WL1 is -V cg , SL is +V s ) It can be seen that erasing memory cell Q m1 When, the storage unit Q m2 It will also be erased at the same time, so this known stacked gate storage element cannot be erased for a single memory cell when it is erased, but can only be erased by one sector (Sector) one sector (Sector) Therefore, there are considerable restrictions on the operation of encoding and erasing components

That is to say, the stacked gate storage element must perform erasing and encoding operations successively to complete the writing of new data, so that all data must be rewritten every time new data is written (because it must be erased first and then encoded) , thus limiting the operating speed of stacked gate storage elements in write mode

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