Scheduler capable of issuing and reissuing dependency chains

Abstract

A scheduler issues instruction operations for execution, but also retains the instruction operations. If a particular instruction operation is subsequently found to be required to execute non-speculatively, the particular instruction operation is still stored in the scheduler. Subsequent to determining that the particular instruction operation has become non-speculative (through the issuance and execution of instruction operations prior to the particular instruction operation), the particular instruction operation may be reissued from the scheduler. The penalty for incorrect scheduling of instruction operations which are to execute non-speculatively may be reduced as compared to purging the particular instruction operation and younger instruction operations from the pipeline and refetching the particular instruction operation. Additionally, the scheduler may maintain the dependency indications for each instruction operation which has been issued. If the particular instruction operation is reissued, the instruction operations which are dependent on the particular instruction operation (directly or indirectly) may be identified via the dependency indications. The scheduler reissues the dependent instruction operations as well. Instruction operations which are subsequent to the particular instruction operation in program order but which are not dependent on the particular instruction operation are not reissued. Accordingly, the penalty for incorrect scheduling of instruction operations which are to be executed non-speculatively may be further decreased over the purging of the particular instruction and all younger instruction operations and refetching the particular instruction operation.

Description

Background of the invention [0001] technical field [0002] The present invention relates to the field of processors, and more particularly to an instruction scheduling mechanism in a processor. [0003] Background technique [0004] Superscalar processors attempt to achieve high performance by issuing and executing multiple instructions per clock cycle and by using the highest possible clock frequency consistent with the design. One method for increasing the number of instructions executed per clock cycle is out of order execution. In out-of-order execution, instructions may be executed in an order other than that stated in the program sequence (or "program order"). Certain instructions near each other in the program sequence may have dependencies that prohibit their simultaneous execution, while subsequent instructions within the program sequence may not have dependencies on previous instructions. Thus, out-of-order execution can increase the performance of the supers...

AI Technical Summary

Problems solved by technology

For aggressive scheduling mechanisms that often suffer from incorrect execution, the performance degradation attributable to these recovery mechanisms can have considerable weight

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