Thin film magnet storage device set with false unit
A storage device and magnetic technology, applied in information storage, static memory, digital memory information, etc., can solve the problems of resistance value fluctuation, difficulty in high-speed and stable data readout, and difficulty in manufacturing pseudo-resistance, and achieve high-speed data. The effect of readout and stable data readout
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Embodiment 1
[0068] refer to figure 1 , according to Embodiment 1 of the present invention, the MRAM device 1 performs random access in response to external control signal CMD and address signal ADD, and inputs write data DIN and outputs read data DOUT.
[0069] The MRAM device 1 includes: a control circuit 5 for controlling the overall operation of the MRAM device 1 in response to a control signal CMD, and a memory array 10 with a plurality of MTJ memory cells arranged in rows and columns. A plurality of write word lines WWL and read word lines RWL are provided corresponding to the rows of the MTJ memory cells, and bit lines BL are respectively provided corresponding to the columns of the MTJ memory cells. The detailed structure of the memory array 10 will be described later.
[0070] The MRAM device 1 further includes: a row decoder 20 , a column decoder 25 , a word line driver 30 , a word line current control circuit 40 , and read and write control circuits 50 and 60 .
[0071] Row de...
Embodiment 2
[0108] In Embodiment 2 of the present invention, a structure of a dummy cell in which an intermediate resistance value is set differently from that of the dummy cell in Embodiment 1 will be described.
[0109] Such as Figure 9 As shown, the dummy cell according to Embodiment 2 of the present invention includes: a tunnel magnetoresistive element TM1, tunnel magnetoresistive elements TR1˜TRn, and an access transistor ATR. In addition, each of the tunnel magnetoresistive elements TR1 to TRn and TM1 has a resistance characteristic of an initial state resistance value Rmin.
[0110] The tunnel magnetoresistive elements TR1 to TRn are connected in parallel with each other. Furthermore, these parallel-connected tunnel magnetoresistive elements TR1 to TRn are connected in series with the tunnel magnetoresistive element TM1 .
[0111] Here, the combined resistance Rdb of the dummy cell according to the second embodiment of the present invention is set as the sum of the combined resist...
Embodiment 3
[0124] with figure 2 Compared with the memory array according to this clear embodiment 3 Figure 11 The difference of the shown memory array is that the dummy cell unit DMCU is provided instead of the dummy cell corresponding to the reference bit line BLref and each memory cell row. All other points are the same, so detailed description will not be repeated.
[0125] Corresponding to the reference bit line BLref and the read word lines RWL1 , RWL2 , and RWLn respectively, dummy cell units DMCU1 , DMCU2 , and DMCUn (hereinafter collectively referred to as dummy cell units DMCU ) are provided.
[0126] The dummy cell unit DMCU1 includes tunnel magnetoresistive elements TR1, TM1 and an access transistor ATRd1. The dummy cell unit DMCU1 includes a magnetoresistive portion DTM1 composed of tunnel magnetoresistive elements TR1 and TM1 connected in series. And, the magnetoresistive part DTM1 is connected in series with the access transistor ATRd1 between the reference bit line Bl...
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