Optimization method for a logical circuit and its device and synthesizer for the logical circuit
A technology for logic circuit optimization, applied in the field of logic circuit optimization and its devices and logic circuit synthesis devices, can solve the problems of reduced motion speed, namely simulation speed, additional signal delay, and smaller circuit scale, to achieve improved Efficiency and high-speed processing effect
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Embodiment approach 1
[0093] FIG. 1 is a block diagram of a logic simulation system according to Embodiment 1 of the present invention.
[0094] As shown in FIG. 1 , this logic simulation system includes a circuit distribution device 1 and a logic simulation device 2 .
[0095] Although not shown in the figure, the logic simulation device 2 includes an FPGA, a memory device, and the like. In addition, although not shown in the figure, a memory device is mounted on the FPGA.
[0096] Here, FPGA is an example of a programmable logic device (Programmable Device) in which a user can freely change circuit operation.
[0097] As the logic simulation device 2, for example, the logic simulation device of FIG. 19 can be used.
[0098] FIG. 2 is a block diagram of the circuit distribution device 1 of FIG. 1 . In FIG. 2, the same parts as those in FIG. 1 are assigned the same symbols.
[0099] As shown in FIG. 2 , the circuit distribution device 1 in FIG. 1 includes: a logic circuit synthesis device 9 , a...
Embodiment approach 2
[0195] The overall structure of the logic simulation system according to Embodiment 2 of the present invention is the same as that in FIG. 1 . Therefore, the logic simulation system of FIG. 1 will be described as the logic simulation system of the second embodiment.
[0196] In addition, the structure of the circuit distribution device 1 of Embodiment 2 is the same as that of FIG. 2 . Therefore, the circuit distribution device 1 of FIG. 2 will be described as the circuit distribution device 1 of the second embodiment.
[0197] In addition, the logic circuit optimization device 8 of Embodiment 2 is the same as that of FIG. 3 . Therefore, the logic circuit optimization device 8 of FIG. 3 will be described as the logic circuit optimization device 8 of the second embodiment.
[0198] FIG. 8 is an explanatory diagram of a logic circuit optimization device 8 according to the second embodiment. FIG. 8( a ) shows a state where the cluster 22 is not loaded into the FPGA 20 , and FIG...
Embodiment approach 3
[0235] In Embodiment 1 and Embodiment 2, optimization processing is performed according to the logic circuit information 4 generated by the logic circuit synthesis device 9 .
[0236] In Embodiment 3, optimization processing is performed before logic synthesis, that is, according to a hardware description language.
[0237] The overall structure of the logic simulation system according to Embodiment 3 of the present invention is the same as that in FIG. 1 . Therefore, the logic simulation system of FIG. 1 will be described as the logic simulation system of the third embodiment.
[0238] In addition, the structure of the circuit distribution apparatus 1 of Embodiment 3 is the same as that of FIG. 2 . Therefore, the circuit distribution device 1 of FIG. 2 will be described as the circuit distribution device 1 of the third embodiment.
[0239] However, the configurations of the logic circuit synthesis device 9 and the logic circuit optimization device 8 of the third embodiment ...
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