Clock synchronizing semiconductor memory equipment

Abstract

A synchronous type semiconductor memory device includes a memory cell array in which memory cells are arranged in a matrix; a row address decoder which activates one of word lines in said memory cellarray based on a row address in response to a word activation signal; a column decoder which activates one of bit line pairs in said memory cell array based on a column address; and a sense amplifiercircuit which amplifies a voltage difference on the activated bit line pair in response to a sense amplifier activation signal. The synchronous type semiconductor memory device further includes a clock data storage section which stores clock data showing a frequency or period of an external clock signal; and a control section which generates the word activation signal based on a row address strobesignal, and generates the sense amplifier activation signal based on the clock data and the row address strobe signal in response to an internal clock signal synchronous with the external clock signal.

Description

technical field [0001] The present invention relates to a semiconductor memory device that operates in synchronization with an external clock signal. Background technique [0002] A conventional clock synchronization type semiconductor memory device is described in Japanese Laid-Open Patent Application (KOKAI Publication No. Hei 8-129887). The structure and operation of a conventional clock type semiconductor memory device will be described below with reference to FIG. 1 . A conventional clock synchronization type semiconductor memory device operates in synchronization with an external clock signal, and has a plurality of memory blocks called banks. Each bank is determined based on a bank address. Control signals and address signals are supplied from external connection terminals in synchronization with an external clock signal. The internal clock signal ICLK is generated in synchronization with an external clock signal supplied from an external connection terminal, and i...

AI Technical Summary

Problems solved by technology

In this case, the desired delay cannot be achieved, and a detection margin is caused to decrease, and stable operation is impossible

[0019] To overcome this problem, while allowing for reduced efficiency, it is necessary to set the time tRCDmin to seven clocks (23.1 ns) or the delay represented by an inverter chain that can generate the delay time independent of generating detection The period of the clock signal used by the circuit of the amplifier to activate the signal SE

However, it is difficult to achieve a stable inverter chain delay in all cases as it varies depending on processing conditions, temperature conditions and voltage conditions

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