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Semiconductor storage device

A technology for memory devices and semiconductors, which is applied in the field of eliminating through current generated during operation and reducing peak current, and can solve the problems of semiconductor memory device failure, source potential reduction, etc., to eliminate through current, reduce peak current, and achieve high-speed characteristics. Effect

Inactive Publication Date: 2005-04-27
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At this time, the source potential decreases, leading to the risk of failure of the semiconductor memory device
[0025] As described above, in order to meet the demand for high-speed read operation, it is difficult to take into account the suppression of shoot-through current or peak current while utilizing the high current supply capability of transistors.

Method used

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  • Semiconductor storage device
  • Semiconductor storage device
  • Semiconductor storage device

Examples

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no. 1 example

[0056] figure 1 is a circuit diagram showing the structure of the word line driving circuit in the semiconductor memory device according to the first embodiment. In this embodiment, transistors having both functions of adjusting timing and limiting current in order to prevent shoot-through current and reduce peak current are provided separately from word line driving unit circuits for individually driving respective word lines. The semiconductor element driven by the word line driving unit circuit of the present invention is, for example image 3 EEPROM shown. Since the structure of the EEPROM has been described above, its explanation is omitted here. The word line driven by the word line driving unit circuit is image 3 "Select Word Line" indicated by reference numeral 2 in . It is not necessary to specifically boost the select word line 2 differently from the control word line 1 .

[0057] figure 1Among them, a TRG signal, a READ signal, an ERASE signal and an address ...

no. 2 example

[0073] see Figure 4 and 5 , the operation and structure of the word line driver circuit in the semiconductor device of this embodiment will be described below. Figure 4 in, with figure 1 Parts of the circuits shown that have the same function are denoted and described with the same reference numerals.

[0074] The basic structure and the figure 1 The basic structure of the circuit shown is the same. But when Figure 4 in, with figure 1 The circuit shown differs in that an Nch transistor MNX for current limitation is also provided on the ground potential side. Then, the potential change becomes slow until the word line potential returns to the ground potential Vss, so that the peak current can be reduced more. That is, in Figure 4 Among them, one or more Nch transistors (MNX) are respectively provided on the ground terminal side of the Nch transistors (MN0˜MNn) of the plurality of word line driving unit circuits.

[0075] The current supply amount of the Nch tran...

no. 3 example

[0080] This embodiment is different from the first and second embodiments in that the operation of each transistor itself forming a word line driving unit circuit for driving a word line can be independently controlled. Two transistors having different current supply amounts are provided as transistors provided on the source potential side (power supply side). These transistors switch appropriately to prevent shoot-through current and reduce peak current.

[0081] Such as Figure 6 As shown, a word line driving unit circuit in the word line driving circuit 120 includes: two Pch transistors (MPR0, MPE0, etc.) and one Nch transistor (MN0, etc.) with different current supply levels, and their drains are connected to Together. Therefore, the word line driving unit circuit of this embodiment is a CMOS push-pull driver. Independent control signals (RA-0, EA-0, EN-0, etc.) are input to the gates of the three transistors respectively. In this way, the operation of each transistor ...

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Abstract

At least one transistor (MPX) is connected between a plurality of word line driving element circuits formed by using CMOS inverters (MP0 and MN0, etc.) and a source potential (Vcc). This transistor (MPX) is independently controlled by a control signal (DECENB) separate from control signals (AB-0 to AB-n) of the word line driving element circuits and has both a through current preventing function by adjusting timing and a peak current reducing function by limiting an electric current. Even when all word lines (SWL0 to SWLn) are driven at the same time, the electric current is limited and the peak current is suppressed.

Description

technical field [0001] The present invention relates to a semiconductor memory device mounted on an IC card, etc., and particularly relates to a technology for eliminating a through current generated during operation and reducing a peak current. Background technique [0002] There are strict requirements for low power consumption of semiconductor memory devices. In particular, in a semiconductor memory device mounted on an IC card or the like, an increase in consumption current or peak current during operation may cause malfunction problems due to heat generation of the IC card or sudden drop in power supply voltage. In recent years, reducing peak current or reducing power consumption has become an important issue. [0003] As a general semiconductor memory device, an EEPROM (Electrically Erasable or Programmable Nonvolatile Memory) will be described below as an example with reference to the drawings. image 3 It is a cross-sectional view of an element showing the structure...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/06G11C8/00G11C8/08G11C16/08G11C16/14H10B69/00
CPCG11C16/08G11C8/08
Inventor 松浦正则
Owner PANASONIC CORP
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