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Bipolar transistor

一种双极晶体管、晶体材料的技术，应用在晶体管、半导体器件、半导体/固态器件制造等方向，能够解决高频区功率增益低等问题，达到低功耗的效果

Inactive Publication Date: 2005-08-17
SHARP KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] Therefore, a conventional HBT has a base resistance r b becomes higher, the problem of low power gain in the high frequency region

Method used

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Experimental program
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no. 1 approach

[0091] Figure 7 A cross-sectional structure diagram of a device to which the first embodiment of the present invention is applied is shown.

[0092] The device has an n-GaN sub-collector layer (layer thickness: 100nm, N d =5×10 18 cm -3 ) 703, the n-In formed in the center region of the upper surface of the sub-collector layer 703 X Ga 1-X N collector layer (layer thickness: 500nm, composition ratio (composition ratio) X=0→0.2, N d =1×10 16 cm -3 ) 704, p-In as the second conductivity type carrier retention layer 0.2 Ga 0.8 N base layer (layer thickness: 25nm, N a =5×10 19 cm -3 ) 705, n-GaN emitter layer (layer thickness: 80nm, N d =5×10 18 cm -3 ) 706 and the p-Al formed in the center region of the upper surface of the emitter layer 706 0.2 Ga 0.8 N gate layer (layer thickness: 50nm, N a =5×10 18 cm -3 )707. n-In X Ga 1-X The In crystal mixing ratio X of the N collector layer 704 is graded such that X=0 on the sub-collector layer side and X=0.2 on the ...

no. 2 approach

[0106] Figure 10 A sectional structural view of a device to which the second embodiment of the present invention is applied is shown.

[0107] The device has an n-GaN sub-collector layer (layer thickness: 100nm, N d =5×10 18 cm -3 ) 1003, the n-In formed in the center region of the upper surface of the sub-collector layer 1003 X Ga 1-X N collector layer (layer thickness: 500nm, In composition ratio X=0→0.2, N d =1×10 16 cm -3 ) 1004, n-GaN emitter layer (layer thickness: 80nm, N d =5×10 18 cm -3 ) 1006 and the p-Al formed in the center region of the upper surface of the emitter layer 1006 0.2 Ga 0.8 N gate layer (layer thickness: 50nm, N a =5×10 18 cm -3 )1007. n-In X Ga 1-X The In crystal mixing ratio X of the N collector layer 1004 is graded such that X=0 on the sub-collector layer side and X=0.2 on the emitter layer side.

[0108] A collector electrode 1009, an emitter electrode 1010, and a gate electrode 1011 are formed similarly to the first embodiment....

no. 3 approach

[0118] Figure 12 A cross-sectional structural diagram of a device to which the third embodiment of the present invention is applied is shown.

[0119] The device has an n-GaN sub-collector layer (layer thickness: 100nm, N d =5×10 18 cm -3 ) 1203, the n-In formed in the central region of the upper surface of the sub-collector layer 1203 X Ga 1-X N collector layer (layer thickness: 500nm, In composition ratio X=0→0.2, N d =1×10 16 cm -3 ) 1204, n-GaN emitter layer (layer thickness: 80nm, N d =5×10 18 cm -3 ) 1206 and the Al formed in the central region of the upper surface of the emitter layer 1206 X Ga 1-X N gate layer (layer thickness: 25nm, Al composition ratio X=0.1→0.3, undoped) 1207 . n-In X Ga 1-X The In crystal mixing ratio X of the N collector layer 1204 is graded so that X=0 on the sub-collector layer side and X=0.2 on the emitter layer side. And, Al X Ga 1-X The Al crystal mixing ratio X of the N gate layer 1207 is graded so that X=0.1 on the emitter...

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Abstract

A bipolar transistor of the present invention comprises a collector layer made of an n-type semiconductor and an emitter layer made of an n-type semiconductor provided on this collector layer. A gate layer for injecting p-type carriers (holes) into the emitter layer is provided on the emitter layer. A p-type carrier retaining layer is formed between the collector layer and the emitter layer. The p-type carrier retaining layer temporarily retains the p-type carriers that are injected from the gate layer into the emitter layer and diffused in the emitter layer and reach the p-type carrier retaining layer. The bipolar transistor has a structure whose performance is not influenced by sheet resistance of the base layer, and is able to exhibit a high current gain even in a high-frequency region.

Description

[0001] This formal application claims priority under 35 U.S.C. §119(a) to Patent Applications P2003-399025 and P2004-323844 filed in Japan on November 28, 2003 and November 8, 2004, respectively, which are incorporated by reference It is incorporated herein in its entirety. technical field [0002] The present invention relates to a bipolar transistor, and more particularly, to a bipolar transistor including a compound semiconductor of a group III element and nitrogen (N) as a material. Background technique [0003] As a type of bipolar transistor containing compound semiconductors of Group III elements and nitrogen (N) as materials, HBT (Heterojunction Bipolar Transistor) made of gallium nitride / aluminum gallium nitride (GaN / AlGaN) material is Well-known (refer to JP2002-368005A). [0004] The HBT on the upper surface of the semi-insulating substrate has n + - gallium nitride (GaN) sub-collector layer (thickness: ~1000nm, concentration of silicon (Si) as n-type dopant: ~6...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/331H01L29/08H01L29/20H01L29/737H01L29/76
CPCH01L29/0817H01L29/2003H01L29/7606H01L29/7371
Inventor 约翰·K·特怀纳姆
Owner SHARP KK
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