Resistive cell structure for reducing soft error rate and inverter and forming method

Abstract

A memory cell for reducing soft error rate and the method for forming same are disclosed. The memory cell comprises a first bit line signal (BL), a second bit line signal complementary to the first bit line signal (BLB), a first pass gate coupled to the BL, a second pass gate coupled to the BLB, a first inverter whose output node receives the BL through the first pass gate, a second inverter whose output node receives the BLB through the second pass gate, a first instrument coupled between the output node of the first inverter and an input node of the second inverter and a second instrument coupled between the output node of the second inverter and an input node of the first inverter, wherein the first and second instruments increase voltage discharge time of the memory cell when voltages at the output nodes of the inverters accidentally discharge.

Description

technical field [0001] The present invention relates to a semiconductor memory, and more particularly to improving the soft error rate with a high-resistance memory cell structure. Background technique [0002] A semiconductor memory is composed of an array of memory cells, and each memory cell stores a bit 1 or 0 in a high or low voltage state. At least every eight bits may constitute a byte, and at least every sixteen bits may constitute a character. In each memory operation cycle, usually at least one byte will be written into or read out of the memory array, and the memory cell is located at the junction of the vertical data line (or bit line) and the horizontal word line, which can be used to read Or write is enabled, and the read or write cycle occurs when a word line and a pair of bit lines are activated, and the memory cell located at the junction of the bit line and the word line can receive written data from the bit line or The read data is sent to the bit lines,...

AI Technical Summary

Problems solved by technology

[0004] However, when the semiconductor memory requires smaller area and higher mobility, the space saving of semiconductor memory becomes more and more important, especially in order to continue to obtain the benefits of size and performance, the memory cell must continue to shrink, however, the memory cell When shrinking, there is a problem. In the static random access memory unit, each inverter storage node is composed of the gate capacitance of the two transistors of the inverter. When the memory cell shrinks, the storage capacitor also shrinks. , the charge used to store data is so small that the electronic noise on the bit or word line or the charge induced by alpha particles (α-particles) becomes very significant in comparison. This electronic noise (which may be The frequency of errors caused by alpha particles) is the soft error rate. When the soft error rate increases, the risk of data integrity loss also increases. Therefore, noise tolerance has become an increasingly important issue in semiconductor memory design. areas of emphasis

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