Method for extracting interconnection parasitic capacitance capable of automatically adapting process characteristic size

A technology of parasitic capacitance and extraction method, which is applied in the direction of circuits, electrical components, electrical digital data processing, etc., can solve problems such as poor self-adaptive ability, and achieve the effect of increasing speed

Inactive Publication Date: 2006-12-20
BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0043] In order to overcome the insufficiency of the current interconnection parasitic

Method used

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  • Method for extracting interconnection parasitic capacitance capable of automatically adapting process characteristic size
  • Method for extracting interconnection parasitic capacitance capable of automatically adapting process characteristic size
  • Method for extracting interconnection parasitic capacitance capable of automatically adapting process characteristic size

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0086] in figure 1 In the illustrated embodiment, the present utility model is executed by the computer in the following steps:

[0087] 1) Read the process feature size S of the input layout from the process file f . figure 2 Schematic diagram of the input layout.

[0088] 2) Scan the entire layout from left to right with a vertical scanning band.

[0089] The width of the scanning zone in this method W sb Set to be proportional to the feature process size of the layout.

[0090] Scanning belt width W in this method sb The recommended value is 60×S f .

[0091] The scanning belt stops at each station. The scanning zone sites are the left and right end points of the conductor edges and the intersections between the conductor edges on the layout. When the scanning belt stays at each station, perform the following actions:

[0092] a) Read in the worksheet of all conductors starting from the right end of the current scan band to the memory.

[0093] b) Delete all conductors that t...

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Abstract

The invention relates to a linked parasitic capacitance extracting method, which can automatically adapt characteristic size, belonging to the integrated circuit computer aided design, wherein arrange the scan band width reduced in ratio with the characteristic size to save memory; reduce the environment conductor horizontally according to the characteristic size after cutting to improve the capacitance extracting speed, and increase the environment conductor longitudinally to improve the extracting accuracy; then divide the edge length from the relative length of characteristic size, to be divided with edge unit to improve the extracting accuracy; at last, solve the discrete edge integral equation to obtain the parasitic capacitance between conductors to improve the property of linked parasitic capacitance extracting program.

Description

technical field [0001] A method for extracting interconnect parasitic capacitances that automatically adapts to process feature sizes belongs to the technical field of extracting parasitic parameters of interconnect lines in chips in integrated circuit computer-aided design (IC-CAD). Background technique [0002] With the development of semiconductor integrated circuit technology, the mature manufacturing process has reached below 90nm, the operating frequency of the circuit is getting higher and higher, the aspect ratio of the interconnection line in the circuit is increasing and the line spacing is decreasing, and the parasitic Electromagnetic field effects have become a major contributor to circuit performance such as time delay, power consumption, power integrity, and signal integrity. Therefore, in the design process of integrated circuits, the influence of interconnection parasitics on circuits must be considered. [0003] The current integrated circuit design first p...

Claims

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Application Information

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IPC IPC(8): H01L21/82G06F17/50
Inventor 戴斌华侯劲松
Owner BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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