Method of manufacturing flash memory device

Abstract

A method of manufacturing a flash memory device. According to the invention, a floating gate can be formed and a distance between cells can be secured sufficiently by using one conductive layer without using a SA-STI process that cannot be applied to the manufacture process of high-integrated semiconductor devices. It is therefore possible to minimize an interference phenomenon between neighboring cells. Furthermore, an isolation film is etched after a photoresist film covering only a high-voltage transistor region is formed, or a gate oxide film is formed after a semiconductor substrate is etched at a thickness, which is the same as that of the gate oxide film of the high-voltage transistor region, so that a step between the cell region and the high-voltage transistor region is the same. Accordingly, the coupling ratio can be increased even by the gate oxide film of the high-voltage transistor region, which is thicker than the tunnel oxide film of the cell region. In addition, damage to a tunnel oxide film, a semiconductor substrate or a floating gate while an isolation film is etched at a predetermined depth in order to control the EFH can be prevented by controlling the EFH in such a manner than conductive layer spacers are formed on sidewalls of the floating gate and the isolation film is further etched.

Description

technical field [0001] The present invention relates generally to semiconductor memory devices, and more particularly, to a method of manufacturing a flash memory device in which interference phenomena between adjacent cells can be minimized in a highly integrated semiconductor device and can be achieved by etching an isolation film with a predetermined thickness To control the effective field height (EFH) and improve the coupling rate. Background technique [0002] NAND flash memory devices use Fowler-Nordheim (FN) tunneling phenomenon to inject electrons into floating gates to implement data programs, thereby achieving large capacity and high integration. [0003] A NAND flash memory device includes a plurality of cell blocks. A cell block includes a plurality of cell strings (strings), wherein a plurality of cells for storing data are connected in series to form a string, and a drain select transistor and a source select transistor are respectively formed between the cel...

AI Technical Summary

Problems solved by technology

However, as the degree of integration of semiconductor devices increases and the cell size decreases, the alignment margin decreases

Therefore, processes using floating gate masks are no longer used

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