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Method for implementing on-chip command cache

An implementation method and instruction technology, applied in the field of hardware implementation of an on-chip instruction cache control system, can solve the problems of long instruction fetch time, poor reliability, and high power consumption, achieve low power consumption, avoid software judgment, and improve reliability Effect

Inactive Publication Date: 2007-07-11
BEIJING MXTRONICS CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This method to realize the control of cache instructions has the disadvantages of high power consumption, long instruction fetch time and poor reliability.

Method used

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  • Method for implementing on-chip command cache
  • Method for implementing on-chip command cache

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Embodiment Construction

[0013] As shown in Figure 1, in the SMDSP signal processor, the instruction cache capacity is 64×32 words, which are divided into two 32 fields, and a 19-bit segment start address register is associated with each segment. Each word in the cache has a corresponding matching flag P bit, and P is 1, which means that the word in the cache is valid, otherwise it is invalid.

[0014] The structure of the instruction cache consists of a cache control register, cache segment start address register, match flag P bit, cache segment word memory, and LRU replacement stack. The cache control register is used to control or indicate the state of the cache. The cache segment start address register The segment address used to store the instruction address, the match flag P bit is used to identify whether a word in the segment has been aligned, the cache segment word memory is used to store instructions, and the LRU replacement stack is used to record the sequence of cache segment replacement. ...

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Abstract

The cache is made by cache control register, cache starting address register, matching mark P position, cache storage and LRU substitute stack. The cache is simple in structure, small in size, low in energy consumption, simple working process based on the structure, easy coordination with other functional parts, improving the reliability of the instruction cache, using hardware substituting stack selecting substituting section name, avoiding software judgment, improving working speed of the instruction cache.

Description

technical field [0001] The invention belongs to the technical field of computers, relates to the design and manufacture of a high-performance signal processor, and in particular to a hardware realization method of an on-chip instruction cache control system. Background technique [0002] Since the invention of computers, the contradiction between computing speed and I / O speed has existed, and cache technology is one of the technologies to solve this contradiction. The traditional cache control system is usually completed by software. For example, the operating system of a PC is responsible for the control and management of the cache. The storage status, data scheduling, replacement strategy, and exception handling of the entire cache are all in charge of the software program in the operating system. Finish. With the advancement of microelectronics manufacturing technology, the computer system can be implemented on a chip, and the cache is also integrated on the chip. How to...

Claims

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Application Information

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IPC IPC(8): G06F12/12G06F12/123
CPCY02B60/1225Y02D10/00
Inventor 车德亮黄玮权海洋
Owner BEIJING MXTRONICS CORP
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