Plating chemistry and method of single-step electroplating of copper on a barrier metal

Abstract

Embodiments of a method of copper plating a substrate surface with a group VIII metal layer have been described. In one embodiment, a method of plating copper on a substrate surface with a group VIII metal layer comprises pre-treating the substrate surface by removing a group VIII metal surface oxide layer and / or surface contaminants and plating the substrate in a copper plating solution comprising about 50 g / l to about 300 g / l of sulfuric acid at an initial plating current higher than the critical current density to deposit a continuous copper layer on the substrate surface. The Pre-treating the substrate can be accomplished by annealing the substrate in an environment with a hydrogen-containing gas environment and / or a non-reactive gas(es) to Ru, by a cathodic treatment in an acid-containing bath, or by immersing the substrate in an acid-containing bath.

Description

CROSS-REFERENCE TO OTHER APPLICATIONS [0001] This application claims the benefit of U.S. provisional patent application Ser. No. 60 / 579,129, entitled “Method Of Barrier Layer Surface Treatment To Enable Direct Copper Plating”, filed on Jun. 10, 2004, and U.S. provisional patent application Ser. No. 60 / 621,215, entitled “Plating Chemistry And Method Of Single-Step Electroplating Of Copper On A Barrier Metal”, filed on Oct. 21, 2004, which is incorporated herein by reference.BACKGROUND OF THE DISCLOSURE [0002] 1. Field of the Invention [0003] Embodiments of the invention generally relate to a plating chemistry and a method of electroplating of copper directly on a barrier metal. [0004] 2. Description of the Background Art [0005] Sub-quarter micron, multi-level metallization is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) semiconductor devices. The multilevel interconnects that lie at the heart of th...

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Problems solved by technology

Many conventional deposition processes do not consistently fill structures in which the aspect ratio exceeds 6:1, and particularly when the aspect ratio exceeds 10:1.

Additionally, as the feature widths decrease, the device current typically remains constant or increases, which results in an increased current density for such features.

Aluminum can also suffer from electromigration, leading to the formation of voids in the conductor.

However, as the interconnect sizes decrease and aspect ratios increase, void-free interconnect feature fill by conventional metallization techniques becomes increasingly difficult using CVD and / or PVD.

However, as the feature sizes become smaller, it becomes difficult to have adequate seed step coverage with PVD techniques, as discontinuous islands of copper agglomerates are often obtained in the feature side walls close to the feature bottom.

When the deposition thickness on the field is reduced to prevent throat closure, ALD and CVD techniques are also prone to generate discontinuities in the seed layer.

These discontinuities in the seed layer have been shown to cause plating defects in the layers plated over the seed layer.

In addition, copper tends to oxidize readily in the atmosphere and copper oxide readily dissolves in the plating solution.

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