Method for applying metal features onto metallized layers using electrochemical deposition and alloy treatment

Abstract

The present invention is directed to a process for producing structures containing metallized features for use in microelectronic workpieces. The process treats a barrier layer to promote the adhesion between the barrier layer and the metallized feature. Suitable means for promoting adhesion between barrier layers and metallized features according to the invention include an acid treatment of the barrier layer, an electrolytic treatment of the barrier layer, or deposition of a bonding layer between the barrier layer and metallized feature. The present invention thus modifies an exterior surface of a barrier layer making it more suitable for electrodeposition of metal on a barrier, thus eliminating the need for a PVD or CVD seed layer deposition process.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a continuation of U.S. application Ser. No. 10 / 470,287, filed Jul. 22, 2003, which is the National Stage of International Application No. PCT / US03 / 00890, filed Jan. 10, 2003, which claims the benefit of U.S. Application No. 60 / 347,520, filed Jan. 10, 2002.FIELD OF THE INVENTION [0002] The present invention is directed to methods for forming metallized structures on barrier layers through electrochemical deposition. BACKGROUND OF THE INVENTION [0003] In the fabrication of microelectronic devices, application of one or more metallization layers is an important step in the overall fabrication process. The metallization may be used in the formation of discrete microelectronic components, but is most often used to provide interconnect components formed on a workpiece, such as a semiconductor wafer. For example, metallized structures are used to interconnect devices of an integrated circuit. [0004] An integrated circuit is ...

AI Technical Summary

Benefits of technology

The present invention provides processes for forming metallized structures in microelectronic workpieces without the need for expensive and time-consuming CVD or PVD methods for depositing seed layers. The processes involve treating the surface of a barrier layer with an acid, electrolytically treating it, or depositing an alloy onto it to improve adhesion between the barrier layer and the metallized features. This results in reduced peeling of the metallized features and improved production yields and reliability of the integrated circuit. The methods are useful in various stages of processing and can be used in both damascene and non-damascene architectures. The invention offers a cost-effective alternative to PVD or CVD methods and increases throughput while reducing costs.

Problems solved by technology

Despite the advantages of copper, it has not been as widely used as an interconnect material as one would expect.

This is due, at least in part, to the difficulty in effectively and economically depositing copper metallization.

Unfortunately, materials used as barrier layers typically do not exhibit the electrical conductive properties necessary to allow for the uniform electrochemical deposition of copper directly onto the barrier layers using conventional gap fill chemistries and processes.

CVD can result in conformal copper coverage over a variety of topological profiles; however, CVD is expensive to carry out and utilizes expensive equipment.

One disadvantage of PVD is that it may result in poor (nonconformal) step coverage when used to fill recessed micro-structures, such as vias and trenches, disposed in the surface of the semiconductor workpiece.

In addition, both PVD and CVD are considered to be relatively slow, thus adversely affecting manufacturing throughput.

However, it has been observed by the present inventors that electrochemical deposition of copper directly onto untreated barrier layers leads to unsatisfactory results, such as poor nucleation and copper peeling due to poor adhesion between the electrodeposited copper and the material of the barrier layer.

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