Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor memory system

Abstract

A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nth signal burst.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a semiconductor memory system. More particularly, the present invention relates to a semiconductor memory system with at least one memory device, a memory controller unit and, an optional register unit. Each of these components comprises an interface circuit and a method for the transfer of write and read data signals among the interface circuits, the data signals each being transferred in signal bursts of a specific burst length. DESCRIPTION OF THE RELATED ART [0002] At present, a separate ECC-module that can detect and possibly correct a channel error or a data error resulting from a DRAM error is provided for the detection or correction of errors in memory modules that are equipped with high-speed semiconductor memory devices. Typically, however, conventional DIMM memory modules for desktop personal computers do not have the capability to detect and correct errors. An additional further module for the detection and / or...

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Benefits of technology

[0005] Accordingly, the present invention aims at facilitating a semiconductor memory system of the aforementioned type and a method for the transfer of write and read data signals among the interface circuits in such a semiconductor memory system, wherein the detection and / or correction of errors at least in the write data signals transferred is achieved without an increase in the number of pins on the semiconductor memory module and / or the memory controller. Additionally, it is possible to synchronize symbols without having to transfer an additional synchronization burst via the bus.

[0007] According to an additional aspect of the invention, the interface circuits are adapted for the transfer of additional bits extending the burst length at least of the write data bursts together with at least every nth signal burst. This extension of the burst length proposed according to an aspect of the present invention allows the additional bits to be used as information on the detection or correction of errors. This design is of additional advantage in that it provides more time for the transfer of command and address information per burst and that, in a memory system with a point-to-point transfer of CA signals (what is called a P2P CA system), it is now, for example, possible to transfer 20 bits per burst per lane. This reduces the necessary number of CA lanes and the number of pins. Since it is important that a predetermined number of CA-commands can be transmitted through a P2P-CA-bus, the extended DQ burst length influences also the transmission on the CA-bus so that more information per burst can be transmitted.

[0008] It is to be noted that the read data may be treated only by an error detection algorithm, wherein the memory controller unit in case of a read error can simply repeat the read operation. Therefore, the extension of the burst length by means of the additional bits may be handled differently for write data and read data bursts so that more additional bits are included in the write data than in the read data bursts. The latter also includes a method wherein only the write data bursts are extended and not the read data bursts. However, it may simplify the circuit design of the interface circuits if the number of the additional bits is made equal for data read and write bursts.

[0009] Furthermore, an additional aspect of the present invention allows the burst length to, for example, 20 bits and uses all or some of the additional bits as synchronization patterns. This permits easy compensation of the overhead caused by the increased operating speed of the interface. What is more, there is no additional synchronization burst that might collide with the write and / or read request burst.

[0010] Thus, the measure proposed by the method according to the invention of extending the burst length by a number of additional bits that can be used as an ECC pattern and / or as a synchronization pattern, can, on the one hand, achieve in the semiconductor memory system according to the invention an effective error detection and / or correction algorithm and, on the other hand, a simplified symbol synchronization that can do without the transfer of a DQS signal or an additional synchronization burst.

[0012] For the purpose of detecting and / or correcting errors, the additional bits contain an error detection and / or correction code concerning the assigned data unit. If, for example, 128 data bits plus 32 additional bits are transferred via an X8 interface in such a semiconductor memory system, 32 bits are available for error correction, thus facilitating a quite effective error correction algorithm. Even if two additional bits are transferred with each burst, it is possible to achieve a highly effective error correction.

Problems solved by technology

Typically, however, conventional DIMM memory modules for desktop personal computers do not have the capability to detect and correct errors.

An additional further module for the detection and / or correction of errors that is not used for the storing of data would excessively increase the cost of such a system.

Since it might collide with read data or write data, the synchronization burst disturbs the data traffic on the bus, and using the transfer of the separate DQS signal for synchronization is always difficult if data transfer rates are high.

Since, however, such a doubling of the pin number is impossible (routing, connector pin count, DRAM ball count, MCH ball count), employing an additional increase in transfer speed is an option.

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