Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel

Abstract

A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor process, and more particularly to a method of fabricating a semiconductor device and a method of adjusting a lattice distance in the device channel region. [0003] 2. Description of the Related Art [0004] In the early days, a metal-oxide-semiconductor (MOS) device is composed of a metal gate electrode, a gate dielectric layer, and a semiconductor substrate. Because the adhesion of most metals to silicon is unsatisfactory, currently, the material of the gate electrode is polysilicon. The application of a polysilicon gate electrode, however, incurs other issues. For example, the device performance decays due to the high resistance of the polysilicon. Accordingly, with the present technology, after forming the device, a salicide process is performed to form metal silicide on the gate electrode and the source / drain regions to reduce the resistance of the device. [0005] In ...

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Benefits of technology

[0012] Accordingly, the present invention is directed to a method of fabricating a semiconductor device to improve device performance.

[0013] The present invention is also directed to a method of adjusting a lattice distance of a device channel region to enhance electron mobility in the channel region.

[0019] The SAB layer of the present invention creates a tension stress which will change the lattice distance in the channel region of the substrate under the gate structure. Accordingly, the electron mobility in the channel region of the substrate under the gate structure is improved. The device performance is also improved. In addition, according to the present invention, a semiconductor process is conducted while the lattice distance is adjusted without additional processes and costs.

[0023] The lattice adjusting layer of the present invention creates a tension stress during the thermal process so that the tension stress changes the lattice distance of the channel region. Accordingly, the electron mobility in the channel region is improved and the device performance is also enhanced.

Problems solved by technology

Because the adhesion of most metals to silicon is unsatisfactory, currently, the material of the gate electrode is polysilicon.

The application of a polysilicon gate electrode, however, incurs other issues.

For example, the device performance decays due to the high resistance of the polysilicon.

However, when the size of the device shrinks, the lattice distance in the channel region 128 seriously affects the electron mobility.

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