Delay distribution calculation method, circuit evaluation method and false path extraction method

Abstract

Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects or elements are input. A vertex is selected for calculation, and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information and the correlation information.

Description

BACKGROUND OF THE INVENTION [0001] The present invention generally relates to technology of evaluating performance of an integrated circuit such as CMOS (Complementary Metal-Oxide Semiconductor) and LSI (Large Scale Integration) in its design. More particularly, the present invention relates to technology of calculation of delay distribution, and removal and extraction of false paths. [0002] In the VLSI (Very Large Scale Integration) design in deep sub-micron era, it is necessary to take variation in manufacturing process into account in advance so that circuits with required performance are produced with high yield. Like the technology such as OPC (Optical Proximity Correction), variation control by mask shape correction has become possible, and is increasingly required in practical applications. Therefore, the future VLSI physical design requires technology of designing a highly integrated, high performance circuit by setting proper design margins for each transistor in view of th...

AI Technical Summary

Benefits of technology

"The present invention provides a method for accurately calculating the delay distribution of an integrated circuit based on actual circuit information. This method takes into account the performance of interconnects and elements in the circuit, and calculates the delay distribution based on correlation information indicating the performance of the interconnects and elements. The delay distribution is then used to evaluate the integrated circuit and extract false paths. The method allows for faster and more accurate evaluation of the integrated circuit's performance."

Problems solved by technology

In delay calculation of a signal z in the circuit 100 as shown in FIG. 9, however, if the delays of signals x and y heavily depend on the delay of a signal b, there is a significant correlation between the delays of the signals x and y. If there is variation in interconnect delay, there is also a correlation between the signal transmission delays of fanout of the signal b. Accordingly, the statistical analysis that does not take correlation into account is likely to be inaccurate.

When delay distribution estimation has poor accuracy, it must be ensured that an integrated circuit will operate in a normal condition even under a plurality of worst conditions which are not likely to occur simultaneously in actual situations, resulting in design including excessive margins.

This unnecessarily increases the area and costs such as power consumption in the designed integrated circuit.

The conventional methods have additional problems.

This results in excessively increased calculation time, degraded accuracy in delay estimation, and the like.

However, if the specification does not allow simultaneous operation of the operating units, these series of operating units correspond to functional false paths.

It is practically impossible for human beings to find logical false paths in view of the large circuit scale.

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