41results about How to "Delayed correction" patented technology

Disclosed is a method, system, and program for generating network performance data. Performance information including a performance time to download a page and execute the page within an application program is received. The received performance information is processed and then performance information output indicating network performance is generated in response to processing the performance information.

A multiband Doherty amplifier having a configuration including a divider which divides an input signal into two, a carrier amplifier which amplifies one of the divided signals, a delay element which delays the other divided signal, a peak amplifier which amplifies the output signal of the delay element, an impedance converter which is connected to an output port of the carrier amplifier and performs predetermined impedance conversion and a combiner which combines the output signals of the peak amplifier and the impedance converter, wherein the electric length of the delay element is the same as the electric length of the impedance converter and the impedance converter has N (N≧2) cascade-connected impedance conversion transmission lines and performs substantially the same impedance conversion at each of the N frequencies.

Two-phase sinusoidal signals QA, QB output from an encoder are interpolated by sample-and-hold (S / H) circuits and A / D conversion (ADC) circuits, and data D is output in accordance with a data request signal RQ from exterior. For this interpolation of encoder output, a direction discrimination up / down counter is arranged near a two-phase square-wave uniform pulse generating circuit, and the data D is latched and output using a signal which is obtained by delaying the data request signal RQ. This can reduce synchronization errors between the data request signal RQ from exterior and the interpolated data, with an improvement in dynamic precision.

A pulse signal delay circuit comprises: a first pulse edge delay circuit for generating a first delay timing signal for sequentially outputting a first edge detection delay timing gained by detecting the rising edge of an input pulse signal and delaying the detection timing by a constant delay time a predetermined number of times; a second pulse edge delay circuit for generating a second delay timing signal for sequentially outputting a second edge detection delay timing gained by detecting the falling edge of the input pulse signal and delaying the detection timing by the delay time the number of times; and a delay pulse signal generating circuit for generating and outputting delay pulse signals rising and falling according to the first and second edge detection delay timings, respectively, from the first and second delay timing signals, the first and second edge detection delay timings delayed the same number of times.

The objective of the invention is to provide an image processing device that can operate at high speed even if input / output with respect to the outside is performed at low speed, and that can fully exploit processibility, by means of input line memory 23 and output line memory 24, which can store image data of one scan line, and are arranged in the input unit and output unit, respectively; the input image data are written in input line memory 23 at the speed of the input image data; the image data that have been written to the input line memory are read at a speed n times faster than the input image data and are sent to processing unit 25 or memory unit 26; processing unit 25 and memory unit 26 receive the image data of one scan line at a speed n times faster than the speed of the input image data, perform a prescribed processing, and then output the processing results at a speed n times faster than the speed of the input image data; the image data output from processing unit 25 or memory unit 26 are selected by selector 29 and written to output line memory 24 at a speed n times faster than the speed of the input image data; the output image data are read in units of one scan line from output line memory 24 at a prescribed speed.

A controller computes a pinching amount of an object caused by a window glass. The controller estimates a prior pinching amount of the object caused by the window glass before the controller computes the pinching amount of the object. The controller confirms occurrence of the pinching of the object based on the computed pinching amount and the estimated prior pinching amount of the object.