39results about How to "Delayed correction" patented technology

Disclosed is a method, system, and program for generating network performance data. Performance information including a performance time to download a page and execute the page within an application program is received. The received performance information is processed and then performance information output indicating network performance is generated in response to processing the performance information.

A metal-insulator-metal capacitor is embedded in an interconnect layer of an integrated circuit (IC). The interconnect layer has a cavity, and the capacitor is formed in the cavity with one of the plates of the capacitor integral with a conductive layer of the interconnect layer, so the capacitor plate electrically communicates with the interconnect layer. The interconnect layer has multiple conductive layers, including a layer, such as aluminum, that is subject to deformation at certain temperatures during fabrication of the IC, and the cavity extends through this layer. A remaining conductive layer of the interconnect layer defines one of the capacitor plates, and a dielectric layer and another capacitor plate are formed thereon within the cavity. Via interconnects of about the same length electrically connect to the top plate and through the interconnect layer to the bottom plate.

A method for synchronizing communications in a wireless communications network wherein time synchronization is performed between a clock master and a clock slave. To achieve synchronization between the clock master and the clock slave, several time synchronization passes are initiated by the clock slave to the clock master. For every pass, each clock slave component generates and transmits a first timing cell containing a transmission time based on the clock slave's component clock, to the clock master. Upon receipt of the first timing cell, the clock master generates and transmits to the clock slave component a second timing cell containing the time the clock master received the first timing cell and the time the clock master transmitted the second timing cell. Upon receipt of the second timing cell, the clock slave component will obtain its reception time and calculate a transmission delay based on the reception time and the timing information contained in the timing cells.

A device designed to validate and transport paper currency in a protected fashion. While being transported, the device monitors for tampering or break-in attempts and subsequently generates warning notifications, or sounds an alarm depending on configuration and the type of tampering detected. The transport case provides end-to-end cash accountability from a location where a bill is inserted into the case, to the bank or cash destination, where the transport case is delivered. Additionally, a docking station accessory is described in which the transport case can be securely fixed while at a point of sale.

The objective of the invention is to provide an image processing device that can operate at high speed even if input/output with respect to the outside is performed at low speed, and that can fully exploit processibility, by means of input line memory 23 and output line memory 24, which can store image data of one scan line, and are arranged in the input unit and output unit, respectively; the input image data are written in input line memory 23 at the speed of the input image data; the image data that have been written to the input line memory are read at a speed n times faster than the input image data and are sent to processing unit 25 or memory unit 26; processing unit 25 and memory unit 26 receive the image data of one scan line at a speed n times faster than the speed of the input image data, perform a prescribed processing, and then output the processing results at a speed n times faster than the speed of the input image data; the image data output from processing unit 25 or memory unit 26 are selected by selector 29 and written to output line memory 24 at a speed n times faster than the speed of the input image data; the output image data are read in units of one scan line from output line memory 24 at a prescribed speed.

A driving aid device for a vehicle comprises a means for imaging and a means for projecting a virtual image in a field of vision of a driver, an opaque screen, arranged in the field of view of the driver, for the formation of a virtual image focused at infinity in the field of vision of the driver of the vehicle, and further comprises means for filtration of zones of high luminous intensity.

A method of manufacturing semiconductor circuits seeks timing closure on a preliminarily select, placed and routed set of cells using a delay for each cell as derated by a derate value obtained from a timing model table having a derate value corresponding to a circuit path depth in the netlist. The derate value for a predetermined number of circuit path depths below k are identical. The derate values are monotonically decreasing for increasing circuit depths in a range between 1.0 and 1.5. Separate timing model tables with differing identical values can be employed for standard and clock tree cells.

A phase delay line comprises a phase-locked loop, a duty-cycle adjusting ring and a voltage equal division to time equal division converter, wherein the phase-locked loop and the duty-cycle adjusting ring form a loop, and one output of the phase-locked loop is connected with the input of the voltage equal division to time equal division converter. The voltage can be precisely divided, and the number of the phases can be easily controlled and expanded. The band gap reference technology enables the working points not affected by the temperature. The negative feedback mechanism of the phase-locked loop determines the period, phase, duty-cycle of the sawtooth wave are same with the reference clock. The ascending and descending time of the sawtooth wave are precisely equal.

Two-phase sinusoidal signals QA, QB output from an encoder are interpolated by sample-and-hold (S/H) circuits and A/D conversion (ADC) circuits, and data D is output in accordance with a data request signal RQ from exterior. For this interpolation of encoder output, a direction discrimination up/down counter is arranged near a two-phase square-wave uniform pulse generating circuit, and the data D is latched and output using a signal which is obtained by delaying the data request signal RQ. This can reduce synchronization errors between the data request signal RQ from exterior and the interpolated data, with an improvement in dynamic precision.

A method, apparatus and computer program product are provided for detecting and powering off unused I/O slots in a computer system. For each of the I/O slots, the current slot is checked to determine if the slot is powered on and unlocked. When the current slot is powered on and unlocked, the current slot is checked to determine if the current slot is a candidate for being powered off. When the current slot is determined to be a candidate for being powered off, then the current slot is powered off and the checking continues with a next one of the I/O slots. Recording the slot as a candidate for being powered off before the slot is actually powered off ensures a proper delay to avoid powering off a slot that is about to be locked, which could cause slot power cycles in quick succession.

A fault detection method for detects, within a semiconductor device, a fault in a delay chain that is provided within the semiconductor device and is made up of delay parts that are each formed by delay cells. The method judges if a fault exists in a first specific delay cell within a first delay part when testing the first specific delay cell, by detecting a first relative delay time between input and output signals of the first specific delay cell, and processing the first relative delay time at a timing based on an output of a delay cell within a second delay part that is provided at a stage preceding or subsequent to the first delay part. The method judges if a fault exists in a second specific delay cell within the second delay part exists when testing the second specific delay cell, by detecting a second relative delay time between input and output signals of the second specific delay cell, and processing the second relative delay time at a timing based on an output of a delay cell within the first delay part.

A technique capable of realizing a power saving in a device for reproducing/recording digital signals by properly controlling a frequency of a clock. The device for reproducing/recording digital signals (device for reproducing an optical disk) includes: a difference comparing circuit for comparing a first parameter (demodulating block counter) updated each time a process for one correcting block is done in a demodulating circuit with a second parameter (error correcting block counter) updated each time a process of one correcting block is done in an error correcting circuit; and a circuit (clock controlling circuit etc.) for switching a frequency of a master clock (MCLK) depending on a comparison result of the difference comparing circuit. Thereby, the frequency of the clock can be switched both of when the demodulation for one correcting block is ended and when the correcting process for one correcting block is ended by using the switched master clock.

A method of aligning a print image of an electrophotographic machine, the method including the steps of determining a power level of a laser beam, sensing a synch position of the laser beam associated with the scan line and varying a delay time before starting the scan line dependent upon the power level and the synch position.

A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.

Provided is voltage/current conversion circuit including: first and second capacitors; first and second resistors each connected to input terminal; first and second current sources; third and fourth resistors connected to current sources; differential amplifier for controlling the current sources; control unit for performing control, in first state, the input terminal is connected to the first and second capacitors; one input of the differential amplifier is connected to the first resistor and output of the first current source; the other input of the differential amplifier is connected to the second resistor and output of the second current source, and in second state, the second capacitor is connected between the output of the first current source and the one input of the differential amplifier, the first capacitor is connected between the output of the second current source and the other input of the differential amplifier.