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Methods for enhancing trench capacitance and trench capacitor

a trench capacitance and capacitor technology, applied in the field of memory fabrication, can solve the problems of trench merging, new materials, sacrificed collars, etc., and achieve the effects of enhancing trench capacitance, increasing processing complexity or cost, and enhancing trench capacitan

Inactive Publication Date: 2008-10-09
CHENG KANGGUO +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach achieves a 12-15% enhancement in trench capacitance by increasing surface area without increasing processing complexity or cost, while being compatible with existing processes and eliminating issues like trench merging, and does not require exotic materials or additional equipment.

Problems solved by technology

This approach, however, requires a sacrificial collar, and is susceptible to trench merging.
Use of new high dielectric constant materials (such as aluminum oxide or hafnium oxide) has also been proposed, but this approach requires new materials and presents numerous integration issues.

Method used

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  • Methods for enhancing trench capacitance and trench capacitor
  • Methods for enhancing trench capacitance and trench capacitor
  • Methods for enhancing trench capacitance and trench capacitor

Examples

Experimental program
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Embodiment Construction

[0015]Turning to drawings, FIGS. 1-5 show one embodiment of a method of forming a trench capacitor 100 (FIG. 5) in a semiconductor-on-insulator (SOI) substrate 102, and FIGS. 6-10 show another embodiment of a method of forming a trench capacitor 200 (FIG. 10) in bulk substrate 202.

[0016]As shown in FIG. 1, in one embodiment, processing begins with SOI substrate 102 including a substrate 104, a buried insulator layer 106 (e.g., silicon oxide (SiO2)) and a semiconductor layer 108 (e.g., silicon (Si), germanium (Ge), silicon germanium (SiGe), etc.). SOI substrate 102 has a pad layer 110 and a hardmask 112. Pad layer 110 may include any now known or later developed pad layer materials such as a silicon nitride (Si3N4) layer and a silicon oxide (SiO2) layer (not individually shown). Hardmask 112 may include any now known or later developed hardmask material such as tetraethyl orthosilicate, Si(OC2H5)4 (TEOS) based silicon oxide (SiO2). Substrate 104 may include, for example, silicon, ger...

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Abstract

Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

Description

[0001]This patent application is a divisional of U.S. patent application Ser. No. 11 / 468,472, filed Aug. 30, 2006, currently pending.BACKGROUND OF THE INVENTION[0002]1. Technical Field[0003]The invention relates generally to memory fabrication, and more particularly, to methods for enhancing trench capacitance and a trench capacitor so formed.[0004]2. Background Art[0005]Capacitance enhancement is essential for trench technology scaling. There are a variety of techniques to increase a surface area of trenches to increase capacitance. In one approach, the trench is formed in a bottle shape to increase the surface area. This approach, however, requires a sacrificial collar, and is susceptible to trench merging. The bottle shape approach also requires extra process steps. In another approach, hemispherical silicon grains (HSG) are formed on a sidewall of the trench to increase its surface area. This approach also requires a sacrificial collar and extra process steps, and further, narro...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/441
CPCH01L28/84H01L29/66181H01L29/945
Inventor CHENG, KANGGUODOBUZINSKY, DAVID M.LI, XI
Owner CHENG KANGGUO