Methods for enhancing trench capacitance and trench capacitor
a trench capacitance and capacitor technology, applied in the field of memory fabrication, can solve the problems of trench merging, new materials, sacrificed collars, etc., and achieve the effects of enhancing trench capacitance, increasing processing complexity or cost, and enhancing trench capacitan
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[0015]Turning to drawings, FIGS. 1-5 show one embodiment of a method of forming a trench capacitor 100 (FIG. 5) in a semiconductor-on-insulator (SOI) substrate 102, and FIGS. 6-10 show another embodiment of a method of forming a trench capacitor 200 (FIG. 10) in bulk substrate 202.
[0016]As shown in FIG. 1, in one embodiment, processing begins with SOI substrate 102 including a substrate 104, a buried insulator layer 106 (e.g., silicon oxide (SiO2)) and a semiconductor layer 108 (e.g., silicon (Si), germanium (Ge), silicon germanium (SiGe), etc.). SOI substrate 102 has a pad layer 110 and a hardmask 112. Pad layer 110 may include any now known or later developed pad layer materials such as a silicon nitride (Si3N4) layer and a silicon oxide (SiO2) layer (not individually shown). Hardmask 112 may include any now known or later developed hardmask material such as tetraethyl orthosilicate, Si(OC2H5)4 (TEOS) based silicon oxide (SiO2). Substrate 104 may include, for example, silicon, ger...
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