Nonvolatile semiconductor memory device

Abstract

A path routing from a write current source supplying a write current through an internal data line, a bit line and a source line to a reference potential except a memory cell is configured to have a constant resistance independent of a memory cell position selected in a memory array, and each of the resistance value of the current path between the memory cell and the write current source and the resistance value of the current path between the selected memory cell and the reference potential node is set to 500Ω or lower. A nonvolatile semiconductor memory device having improved reliability of data read / write is achieved.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a nonvolatile semiconductor memory device, and particularly to a construction for improving reliability of write and read data of a phase change memory including memory cells each having a data storing element which selectively attains a crystalline state (polycrystalline state) and an amorphous state in accordance with stored data.[0003]2. Description of the Background Art[0004]Nonvolatile memories storing information in a nonvolatile manner have been widely employed in application of portable equipment and others. As such nonvolatile memories, there are a flash memory storing information by storing charges on a floating gate of a stacked gate transistor, and a memory utilizing a resistance value change type memory cell having a resistance value of a memory element changed according to stored information. As the resistance value change type memories, there are known various memories suc...

AI Technical Summary

Benefits of technology

The solution enables fast and accurate data reading and writing by reducing interference between memory cells, maintaining data integrity, and allowing reliable operation even under low power supply voltages, while minimizing the dependency on the position of selected memory cells within the array.

Problems solved by technology

When the source line is shared between the memory cells from which the data are concurrently read, read currents flow in parallel through these selected memory cells, and may cause mutual interference between the selected memory cells through the shared source line, so that accurate reading may be difficult.

When the large current raises the source line potential, the raised potential restricts the read currents of the other selected memory cells, which causes a problem of increase in access time or occurrence of erroneous reading.

Accordingly, a read current path is associated with a stray capacitance of write circuitry for supplying the large write current, resulting in a problem that read current can not be changed fast.

In this construction, however, two variable resistance elements store data of one bit, so that a storage capacity is small.

Since the read current flows through the reference cell, this read current may cause read disturbance, that the state of the phase change material element slowly changes from the amorphous state to the crystalline state, leading to a problem that an accurate reference current cannot be produced.

Consequently, a problem arises that a margin for the sense operation in data reading lowers, and accordingly, fast reading of accurate data cannot be achieved.

In this case, therefore, when the lengths of the internal data line, bit line and source line included in the write current path change depending on the selected address position, the total resistance value of the write current path changes to change the write current value, which results in a problem that a margin in the data write operation is impaired and data writing cannot be performed fast.

For example, a large write current flows to the shared source line via the memory cell of the smallest resistance value, to raise the potential on the shared source line to restrict the write currents of other memory cells, resulting in an erroneous data writing or others.

Further, the write current needs to be large, but a sufficiently large write current cannot flow due to the electric resistance of the shared source line, which may cause erroneous writing.

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