Processor architecture for executing transfers between wide operand memories

Abstract

A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Description

RELATED APPLICATIONS[0001]This application is a continuation of U.S. patent application Ser. No. 11 / 346,213 filed Feb. 3, 2006, which is a continuation of U.S. patent application Ser. No. 10 / 616,303, now U.S. Pat. No. ______, which is a continuation of U.S. patent application Ser. No. 09 / 922,319, filed Mar. 24, 2000, now U.S. Pat. No. 6,725,356 which is a continuation of U.S. patent application Ser. No. 09 / 382,402, filed Aug. 24, 1999, now U.S. Pat. No. 6,295,599, which claims the benefit of priority to Provisional Application No. 60 / 097,635 filed on Aug. 24, 1998. Each of the above applications and / or patents are herein incorporated by reference in their entirety.FIELD OF THE INVENTION[0002]The present invention relates to general purpose processor architectures, and particularly relates to wide operand architectures.BACKGROUND OF THE INVENTION[0003]Communications products require increased computational performance to process digital signals in software on a real time basis. Incre...

AI Technical Summary

Benefits of technology

[0021]When an extract is controlled by a register, the size of the result can be specified, allowing rounding and limiting to a smaller number of bits than can fit in the result. This permits the result to be scaled for use in subsequent operations without concern of overflow or rounding. As a result, performance is enhanced. In those instances where the extract is controlled by a register, a single register value defines the size of the operands, the shift amount and size of the result, and the rounding control. By placing such control information in a single register, the size of the instruction is reduced over the number of bits that such an instruction would otherwise require, again improving performance and enhancing processor flexibility. Exemplary instructions are Ensemble Convolve Extract, Ensemble Multiply Extract, Ensemble Multiply Add Extract, and Ensemble Scale Add Extract. With particular regard to the Ensemble Scale Add Extract Instruction, the extract control information is combined in a register with two values used as scalar multipliers to the contents of two vector multiplicands. This combination reduces the number of registers otherwise required, thus reducing the number of bits required for the instruction.

Problems solved by technology

In addition, several classes of instructions will be provided which cannot be performed efficiently if the source operands or the at least one result operand are limited to the width and accessible number of general purpose registers.

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