Method and apparatus for supporting delay analysis, and computer product

Abstract

A delay distribution of a partial path that passes through a node to which a plurality of signals is input and for which an estimation in a statistical MAX is predicted to be large, that is present on a critical path having large influence on a circuit delay, and that has high possibility of improving the circuit delay, among nodes in a circuit graph is calculated by the Monte Carlo simulation instead of the block based simulation, thereby increasing speed and accuracy of delay analysis.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2007-302775, filed on Nov. 22, 2007, the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a technology of delay analysis support for circuits.[0004]2. Description of the Related Art[0005]With miniaturization of large-scale integrations (LSI) in recent years, influence of statistical factors, such as process variation, reduction of supply voltage, and crosstalk, has become large, and a variation in circuit delay has been increasing. In a conventional static timing analysis (STA), a delay margin is secured for such a variation in circuit delay. Because of increase of the delay margin, timing design has become difficult.[0006]For this reason, a demand for statistical static timing analysis (SSTA) increases in which an unne...

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Benefits of technology

[0011]It is an object of the present invention to at leas

Problems solved by technology

With miniaturization of large-scale integrations (LSI) in recent years, influence of statistical factors, such as process variation, reduction of supply voltage, and crosstalk, has become large, and a variation in circuit delay has been increasing.

Because of increase of the delay margin, timing design has become difficult.

On the other hand, by the block-based analysis, it is considerably difficult to acquire a true delay distribution of a node at which multiple signals run together.

However, an estimation error by the statistical MAX operation can become large.

As a result, accuracy of the delay analysis is deteriorated.

However, in the conventional technique described above, to accurately acquire the delay distribution of the node at which multiple signals run together, complicated calculation is required, and the high speed property of the block-based analysis can be set off thereby.

As a result, time required for the delay analysis increases, leading to increased design period.

Accordingly, application to a large scale circuit is difficult.

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