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Nested Virtualization Performance In A Computer System

a computer system and nested virtualization technology, applied in the field of hardware-assisted virtualization, can solve the problems of prohibitively slow mechanism and unacceptably high performance impact on certain workloads, and achieve the effect of improving the performance of nested virtualization

Inactive Publication Date: 2012-07-26
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach significantly reduces overhead by enabling direct, non-privileged access to the secondary control structure, enhancing the performance of nested virtualization by eliminating the need for repeated invocations of the primary VMM and minimizing the performance impact on workloads.

Problems solved by technology

The high frequency of virtualization instructions in the critical code paths can make this mechanism prohibitively slow.
This is complicated and may have an unacceptably high performance impact on certain workloads.

Method used

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  • Nested Virtualization Performance In A Computer System
  • Nested Virtualization Performance In A Computer System
  • Nested Virtualization Performance In A Computer System

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0015]Turning now to the figures, wherein like reference numerals represent like elements in all of the several views, FIG. 1 illustrates an example computer system 2 configured to support nested virtualization. The system 2 includes a physical machine 4 that incorporates at least one CPU (Central Processing Unit) 10 and a memory 12 operatively coupled to the CPU 10. The CPU is an integrated circuit that may be implemented as an execution core of a single-core or multi-core microprocessor, or in any other type of instruction processing device, such as general purpose processor, a micro-controller, a signal processor, etc. The CPU 10 may implement the x86 architecture, but this is not a requirement for practicing the nested virtualization technique disclosed herein. The memory 12 may be implemented using any type of computer readable storage medium capable of storing program instructions and data. Example memory types include, but are not limited to, static or dynamic random-access m...

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Abstract

A virtualization architecture for improving the performance of nested virtualization in a computer system. A virtualization instruction reads or writes data in a control structure used by a virtual machine monitor (VMM) to maintain state on a virtual machine (VM) to support transitions between a root mode of operation of a CPU in which the VMM executes and a non-root mode of operation of the CPU in which the VM executes. A privileged data access is made to a primary control structure according to the virtualization instruction if the CPU is in the root mode. A non-privileged data access is made to a secondary control structure according to the virtualization instruction if the CPU is in the non-root mode and a secondary control structure field in the primary control structure is enabled.

Description

BACKGROUND[0001]1. Field of the Invention[0002]The present invention relates to hardware-assisted virtualization of data processing resources. More particularly, the invention concerns improvements in providing multiple layers of hardware-assisted virtualization.[0003]2. Description of the Prior Art[0004]By way of background, modern microprocessors, such as those based on the x86 architecture, include hardware-assisted support for virtualization. A set of virtualization instructions allows a hypervisor to operate in a super-privileged root mode while running guest operating systems and application software in non-root mode at their normal privilege levels. The x86 hardware virtualization feature is presently not virtualized itself. This may prevent an x86 root-mode hypervisor from efficiently running a non-root mode hypervisor as a guest, a concept known as nested or layered virtualization. The two main techniques to address this shortcoming are trap-and-emulate and dynamic translat...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F9/312
CPCG06F9/45558G06F2009/45566
Inventor DAY, II, MICHAEL D.HARPER, RYAN A.LIGUORI, ANTHONY N.
Owner INT BUSINESS MASCH CORP
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