Method of global design closure at top level and driving of downstream implementation flow

Abstract

System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files. Using the results of this top-down global design-closure method the designers can use the generated floor-plan to guide downstream tools to achieve predictable and correlatable design implementation.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This patent application claims priority under 35 U.S.C. 119(e) from prior U.S. provisional application No. 61 / 806,906, filed Mar. 31, 2013.TECHNICAL FIELD[0002]The present invention relates to systems and methods for completing design closure for system-on-chip (SoC) integrated circuits. The invention specifically relates to a top-down design method and system that allows for fast and efficient design closure, while meeting area, timing, congestion and power constraints, by enabling physical planning early in the design cycle of the SoC.BACKGROUND ART[0003]Today's SoCs are very large and complex with large number of IP blocks, memory blocks, and logic connected using one or more interconnect bus fabric. Many of the IP blocks are third party IPs with RTLs licensed from vendors. These base IPs are then customized or hardened to suit the use in the SoC by instantiation of additional memory blocks, adding pipelining to speed up the operation, ...

AI Technical Summary

Benefits of technology

[0010]The final floorplan which meets area, timing, congestion and power constraints is used to generate synthesis constraints specific to each cluster, as well as overall placement and routing guidance for hard macros and clusters. The implementation guidance based on early design closure enables efficient implementation for both the SoC as well as underlying IP blocks.

[0011]The method provides a capability for planning for design-closure from the start of a design in a top-down manner by:1. Enabling the floor planning by a process of clustering wherein the logical design hierarchy is converted to a physical hierarchy by breaking down the synthesized logical hierarchy to a physical hierarchy of standard cell clusters;2. Providing a visual capability to the designers to follow data flow within the design using cluster layout;3. Floor-planning, shaping and placing the clusters along with the placement of memory macros, black or gray box logic, and special clusters such as I / O logic or glue logic clusters to enable the analysis of the global interconnects of the design and to allow for early optimization and validation of the design closure based on the global interconnect;4. Enabling grouping and placement of hard macros (IPs) based on connectivity timing and power constraints along with the placement and shaping of the logic clusters;5. Using small groupings or clusters of locally connected logic to define optimum placement of the design for reducing global routing needs and improving timing;6. Dynamically sizing the cluster to adjust its utilization based on the internal complexity of the cluster;7. Separating the timing paths in the design into global timing paths (inter-cluster) and local timing paths (intra-cluster) to optimize each independent of the other; and8. Providing up-front capability to optimize the global routing needed, minimize clock tree distribution, and reducing re-entrant and snaking routes to optimize timing and congestion closure.

[0012]The method also enables early back-end optimization by:1. Mapping data flow of the developed physical hierarchy into a floor plan in which clusters are shaped and placed optimally and I / O clusters and glue logic clusters are placed in a distributed fashion meeting the constraints of the design;2. Estimating wire delays of long paths based on routing estimates and optimizing cluster placement to reduce wire delays and achieve timing closure;3. Iterating the floor plan to reduce global timing issues and meet the timing constraints; and4. Fixing the location of hard macros and cluster locations enabling generation of a physical topology constraint file that is used for place and route, that is physical synthesis of back end.

Problems solved by technology

Today's SoCs are very large and complex with large number of IP blocks, memory blocks, and logic connected using one or more interconnect bus fabric.

These IPs typically end up having complexities similar to the SoC itself but on a smaller scale, in that these can have 10 s of millions of placeable instances, hundreds of memory blocks or macros, multiple clock trees with differing clock frequencies and multiple power domains.

The teams that work on hardening and design closure of the IPs and SoCs typically are different from the RTL designers and have limited access and knowledge of the internal structure of the IP.

This makes the process of design closure very complex and time consuming.

The current circuit design flows typically do not allow design closure and validation before the detailed place and route is complete even though the critical paths are typically the global routes within the SoC 100.

Though there have been programs that enable wire modeling providing delay estimates of interconnects, these have not been accurate enough to provide estimates that are realistic below 45 nm technology node as the wiring parasitic dominate the delays.

This makes it impossible to have design closure and validation without completing the final physical planning and place and route of the SoC 100.

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