Controller, semiconductor memory system and operating method thereof

Abstract

An operating method of a memory controller includes performing a soft read operation to read data stored in a semiconductor memory device using a soft read voltage, performing a soft decision ECC decoding operation to the read data based on a first log likelihood ratio (LLR) value, and performing the soft decision ECC decoding operation to the read data based on a second LLR value when the soft decision ECC decoding operation based on the first LLR value fails. The first and second LLR values are selected between a default LLR value and an updated LLR value. The updated LLR value is generated on a basis of numbers of error bits and non-error bits of the read data, which are obtained through the soft decision ECC decoding operation to the read data.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority of Korean Patent Application No. 10-2015-0032598, filed on Mar. 9, 2015, which is incorporated herein by reference in its entirety.BACKGROUND[0002]1. Field[0003]Various exemplary embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a controller, a semiconductor memory system and an operating method thereof.[0004]2. Description of the Related Art[0005]Semiconductor memory devices are generally classified into volatile memory devices, such as dynamic random access memory (DRAM) and static RAM (SRAM), and nonvolatile memory devices, such as read only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), ferromagnetic RAM (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM) and flash memory.[0006]Volatile memory devices lose their data without a constant source of po...

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