Method and apparatus for high speed clock distribution

Abstract

A clock distribution network includes receiving a remote voltage signal; transmitting the remote voltage signal into a local voltage signal using a current-mode transmission scheme that comprises a cascade of a voltage-to-current driver, a transmission line, a current buffer, and a LC (inductor-capacitor) tank; transmitting the local voltage signal into a first destination voltage signal using a voltage-mode transmission scheme that comprises a cascade of a first capacitively driven wire and a first inverter buffer; and transmitting the local voltage signal into a second destination voltage signal using a voltage-mode transmission scheme that comprises a cascade of a second capacitively driven wire and a second inverter buffer.

Description

BACKGROUND OF THE DISCLOSUREField of the Disclosure[0001]The present disclosure generally relates to clock distribution, and more particularly to a method and circuit for transmitting a high-speed clock over relatively long transmission lines.Description of Related Art[0002]A clock is a voltage signal that oscillates between a low level and a high level. Clocks are widely used in synchronous digital circuits for coordinating actions of said synchronous digital circuits. An integrated circuit that contains a plurality of synchronous digital circuits usually has a clock generation circuit, e.g. a phase lock loop, configured to generates a clock, which usually needs to be transmitted through a transmission line to said plurality of synchronous digital circuits to coordinate actions thereof. In a case where the clock generation circuit and a synchronous digital circuit that needs to receive the clock from the clock generation circuit are physically separated by a long distance, the tran...

AI Technical Summary

Benefits of technology

The patent describes a system for distributing clock signals using a network of components such as voltage-to-current drivers, transmission lines, current buffers, and LC tanks. The system allows for the transmission and amplification of the clock signals through the network, resulting in a final output at the destination. The patent also describes a method of clock distribution using current-mode and voltage-mode transmission schemes. The technical effects of the patent include improved clock distribution and amplification, which can improve the accuracy and reliability of clock signals in electronic devices.

Problems solved by technology

In a case where the clock generation circuit and a synchronous digital circuit that needs to receive the clock from the clock generation circuit are physically separated by a long distance, the transmission of the clock might be challenging.

The-long distance transmission of the clock usually suffers a large insertion loss, resulting in a weak signal on the receiving end.

The problem worsens when the clock is a high-speed clock, since the insertion loss of a transmission line increases as a frequency of the transmitted signal increases.

For a 2 mm transmission line fabricated on a silicon substrate using a CMOS (complementary metal oxide semiconductor) process, a typical insertion loss for a 15 giga-Hertz clock is 3 dB and that is considered a large insertion loss.

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