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Semiconductor device comprising eFUSES of enhanced programming efficiency

a technology of enhanced programming efficiency and semiconductor devices, which is applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of enhanced power consumption, high complexity of circuits, and exponential increase, and achieve the effect of increasing current density

Active Publication Date: 2012-09-18
GLOBALFOUNDRIES US INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention relates to semiconductor devices and methods for forming them. The invention provides electronic fuses that have increased tolerance to programming voltages and can reliably achieve a programmed state. The electronic fuses have a non-linear portion that generates a zone of increased current density, which enables the use of lower voltages and reduces the size of the fuses. The invention also includes methods for designing and using the electronic fuses, as well as semiconductor devices that include the electronic fuses. The technical effects of the invention include increased programming reliability and reduced size of the electronic fuses.

Problems solved by technology

For this reason, highly complex circuits have been developed, which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC).
However, the shrinkage of the gate dielectric thickness may be associated with an exponential increase of the leakage currents, which may directly channel through the thin gate dielectric material, thereby contributing to enhanced power consumption and thus waste heat, which may contribute to sophisticated conditions during operation of the semiconductor device.
Moreover, charge carriers may be injected into the gate dielectric material and may also contribute to a significant degradation of transistor characteristics, such as threshold voltage of the transistors, thereby also contributing to variability of the transistor characteristics over the lifetime of the product.
Consequently, the combination of the various circuit portions in a single semiconductor device may result in a significant different behavior with respect to performance and reliability, wherein the variations of the overall manufacturing process flow may also contribute to a further discrepancy between the various circuit portions.
However, with the continuous shrinkage of critical device dimensions in sophisticated semiconductor devices, the reliability of programming corresponding electronic fuses may require tightly set margins for the corresponding voltages used to program the electronic fuses, which may not be compatible with the overall specifications of the semiconductor devices or may at least have a severe influence on the flexibility of operating the device.
As previously discussed, a corresponding required degree of reliability in detecting the programmed state may require sufficiently high programming voltages, which may not be compatible with the supply voltages used for sophisticated devices.

Method used

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  • Semiconductor device comprising eFUSES of enhanced programming efficiency
  • Semiconductor device comprising eFUSES of enhanced programming efficiency
  • Semiconductor device comprising eFUSES of enhanced programming efficiency

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Embodiment Construction

[0031]Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

[0032]The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details ...

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Abstract

In sophisticated integrated circuits, an electronic fuse may be formed such that an increased sensitivity to electromigration may be accomplished by including at least one region of increased current density. This may be accomplished by forming a corresponding fuse region as a non-linear configuration, wherein at corresponding connection portions of linear segments, the desired enhanced current crowding may occur during the application of the programming voltage. Hence, increased reliability and more space-efficient layout of the electronic fuses may be accomplished.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to forming electronic fuses for providing device-internal programming capabilities in complex integrated circuits.[0003]2. Description of the Related Art[0004]In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like are formed on a single chip area. Typically, feature sizes of these circuit elements are steadily decreasing with the introduction of every new circuit generation to provide currently available integrated circuits with an improved degree of performance in terms of speed and / or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size is c...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L21/82
CPCH01L23/5256Y10T29/49107H01L2924/3011H01L2924/0002H01L2924/00
Inventor AUBEL, OLIVERPOPPE, JENSKURZ, ANDREASBOSCHKE, ROMAN
Owner GLOBALFOUNDRIES US INC
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