Error recovery circuit oriented to CPU pipeline

Abstract

Disclosed is an error recovery circuit facing a CPU assembly line, comprising: on-chip monitoring circuits (1), an error signal statistics module (2), a voltage frequency control module (3), an error recovery control module (4), an in-situ error recovery module (5) and an upper-layer error recovery module (6), wherein each of the on-chip monitoring circuits (1) is integrated at the end of each stage of assembly lines of the previous N−1 stages of assembly lines of a CPU kernel with an N-stage assembly line structure, so as to monitor the time sequence information about each clock period of an operating circuit, wherein N is a positive integer which is greater than or equal to 3 and less than 20. The present invention provides the on-line time sequence monitoring on the CPU kernel with N stages of assembly lines to search for the lowest possible operating voltage of the circuit, and to reduce the margin of the operating voltage reserved for the circuit in the design stage, thereby significantly reducing the power consumption of the circuit and improving the energy efficiency of the circuit.

Description

I. TECHNICAL FIELD[0001]The present invention relates to an error recovery circuit oriented to CPU pipelines, in particular to an error recovery circuit which is based on on-chip error monitoring, oriented to CPU pipelining applications, and switchable according to the monitoring result, and belongs to the integrated circuit design field.II. BACKGROUND ART[0002]As transistors become smaller and smaller, the number of transistors integrated on unit area has increased rapidly, and the power consumption of integrated circuit has become a factor that is of the same significance as functionality and area. A dynamic voltage and frequency scaling (DVFS) technique, which aims at reducing the power consumption of circuit, has become an important power saving technique gradually owing to its remarkable effect.[0003]DVFS depends on the monitoring of the operating state and performance of the main circuit. A main system-level monitoring means is to utilize sensors. Though such a means, it can r...

AI Technical Summary

Benefits of technology

The present invention provides an online time sequence monitoring method for a CPU core having an N-stage pipeline, which reduces the operating voltage margin reserved for the circuit in the design stage by finding out the lowest permissible operating voltage of the circuit, and thereby greatly reduce the power consumption and improve the energy efficiency of the circuit. The invention also provides a method that involves two different error recovery modes: local error recovery mode and global error recovery mode, which allows for flexible selection of the appropriate error recovery mode for the system according to the system requirement and operating state of the circuit, and achieves higher throughput and higher power consumption reduction benefit.

Problems solved by technology

Though such a means, it can reflect the current operating condition of the system to some degree, but off-chip monitoring often depends on the accuracy of the sensors and it is difficult to choose reliable monitoring points.

Therefore, it is difficult to reflect the actual condition of each part in a chip by off-chip monitoring.

Though a method that involves inserting critical units and replicating critical paths in a chip, it can reflect the variations of global parameters in the chip authentically, but the replicates and critical units and paths are not in the same on-chip environment, it is not sensitive to the variations of local parameters such as local noise and process fluctuations, consequently, it is difficult to reflect the actual condition of the circuits, and the voltage scaling effect is severely compromised.

In case the voltages drops to be lower than a threshold voltage below which the circuit is error-prone, timing violations may occur in the on-chip logic.

There is a risk of system errors when the lowest voltage point at any time of system operation is sought dynamically.

The on-chip monitoring unit that employs such an error recovery approach is complex in structure, and the power consumption of the monitoring unit itself is high; in addition, if circuit errors occur frequently owing to the operating conditions such as operating voltage, frequency, and temperature, etc., for each clock cycle that involves errors, the CPU clock has to be suspended for a cycle to wait for error signal recovery.

Consequently, the cost of error recovery is high, the system throughput is severely compromised, and the power saving effect is not satisfactory.

Such a recovery approach consumes N cycles in one run.

Therefore, if the system error ratio is high, the global error recovery approach has smaller impact on the system throughput and has a better power consumption reduction effect; however, if the system error ratio is low, the cost of recovery is high and the power consumption reduction effect is not significant.

At present, the recovery of DVFS circuit solely utilizes one of the approaches described above, and its system applicability is very limited.

For applications that require a wide frequency range and involve high error ratio variations, it is difficult to attain optimal system throughput and power consumption in single error recovery approach.

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