Semiconductor electrostatic discharge protection circuit, ESD protection semiconductor device, and layout structure of ESD protection semiconductor device

Abstract

An electrostatic discharge protection semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate and spaced apart from the first well, a gate formed on the substrate and positioned in between the first well and the second well, a drain region formed in the first well, a source region formed in the second well, a first doped region formed in the first well and adjacent to the drain region, and a second doped region formed in the first well and spaced apart from both the first doped region and the gate. The first well, the drain region, and the source region include a first conductivity type, the second well, the first doped region and the second doped region include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to an electrostatic discharge (hereinafter abbreviated as ESD) protection circuit, an ESD protection semiconductor device, and a layout structure of an ESD protection semiconductor device, and more particularly, to an ESD protection circuit including an ESD protection semiconductor device and a layout structure of the ESD protection semiconductor device.[0003]2. Description of the Prior Art[0004]With the advancement of technology, the development of semiconductor process is ongoing. A modern chip is therefore allowed to have a plurality of various electronic circuits configured within. For example, the integrated circuits (hereinafter abbreviated as ICs) integrated in the chip(s) can be divided into core circuits and input / output (hereinafter abbreviated as I / O) circuits, and the core circuits and the I / O circuits are respectively driven by different power supply sources with different volt...

AI Technical Summary

Benefits of technology

The present invention provides an ESD protection semiconductor device and layout structure that includes first and second doped regions within a first well. This results in a parasite BJT and a SCR that work together to provide an ESD protection circuit with higher holding current and lower trigger voltage, while improving latch-up immunity without increasing layout area. The BJT always turns on first in an ESD event, bypassing a portion of the ESD current, and the SCR is then turned on to significantly increase the holding current of the ESD protection circuit.

Problems solved by technology

As products based on ICs become more delicate, they also become more vulnerable to the impacts from external environment.

And thus, it is assumed that ESD is a constant threat to the modern electronics.

However, a problem arises when the holding voltage is lower than the operating voltage (Vdd) at which the ESD protection device / circuit operates: it is easily latched-up and thus cannot provide protection to the internal circuit.

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