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Package method for multiple chip integrated circuit

A technology of integrated circuits and packaging methods, which is applied in the direction of circuits, electrical components, and electrical solid devices, and can solve problems such as undesired chips, lack of chip equipment and capabilities, reduced installation density, chip costs, and production process requirements, etc., to achieve The effect of broadening functions and reducing production process requirements

Inactive Publication Date: 2009-12-16
SHANGHAI GOTOP SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This limits the application range of "system-in-package" chips. The limitation is that many complete machine factories that can assemble chips with metal pins do not have the equipment and ability to install chips packaged with ball grid arrays; at the same time, a large number of low-end electronic products In consideration of reducing mounting density, chip cost and production process requirements, it is not desirable to use ball grid array packaged chips

Method used

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  • Package method for multiple chip integrated circuit
  • Package method for multiple chip integrated circuit
  • Package method for multiple chip integrated circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0029] The multi-chip integrated circuit packaging method of the present invention comprises the following steps:

[0030] a, using a metal lead frame as the carrier of the multi-chip package;

[0031] b, using a silicon wafer as a substrate to form a silicon wafer substrate, and setting wiring for chip interconnection on the silicon wafer substrate;

[0032] c, placing a silicon wafer substrate on a metal lead frame;

[0033] d, stacking multiple chips to be packaged on the silicon wafer substrate;

[0034] e. Interconnect or connect multiple chips to be packaged with gold wires to the silicon wafer substrate;

[0035] f, and then connect the silicon chip substrate and the metal lead frame with gold wires;

[0036] g. Plastic-encapsulate the chip, the silicon substrate, and the metal lead frame.

[0037] In step d, when stacking multiple chips on the silicon substrate, the multiple chips can be stacked in one or several layers.

[0038] When multiple chips stacked on the...

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Abstract

This invention discloses a multi-chip IC package method and its structure. The method includes: applying a metal pin frame as the carrier of the chip package, applying the silicon chips as the base plate to form a silicon chip base plate and setting interconnected layout by the chips, putting silicon chips on the frame as the base plate and laminating under-packaged multiple chips on the base plate to be interconnected or connected to the silicon base plate by wires then to connect the base plate and the metal pin frame with wires. The chips, base plate and the pin frame are packaged by plastics, which breaks through present form of ball-grating array to realize the package form of metal pins.

Description

technical field [0001] The invention relates to the packaging of integrated circuit chips, more specifically to a multi-chip integrated circuit packaging method. Background technique [0002] At present, in the packaging of integrated circuit chips, a "system in package (SIP)" scheme that interconnects multiple bare chips into a system and assembles them in a single package is increasingly valued. Although the "system on chip (SOC)" solution can design and manufacture multiple chip functions on a single die, it also has the advantages of "system in package (SIP)" in providing circuit board mounting density and reliability, but it is different from "system Compared with "system in package (SIP)", the "system on chip (SOC)" solution has the limitations of long design cycle, high research and development costs, and difficulty in integrating high frequency, high voltage and other circuits. Therefore, "system in package (SIP)" does not have the above Shortcomings have to develop...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60H01L25/065H01L21/50
CPCH01L2924/15311H01L2924/10253H01L2224/48091H01L2224/48247H01L2924/14H01L24/73H01L2224/32145H01L2224/32225H01L2224/32245H01L2224/48137H01L2224/48227H01L2224/73265H01L2924/00014H01L2924/00H01L2224/48145H01L2924/00012
Inventor 崔巍
Owner SHANGHAI GOTOP SEMICON