Method of etching low dielectric constant films

Abstract

A method for etching a low dielectric material to form sidewall spacers including forming a gate electrode on a substrate, forming a source region and a drain region disposed in a substrate, forming a low dielectric constant film over the gate electrode, source region, and drain region, and etching the low dielectric constant film to form sidewall spacers. The method also includes a first part of the etch process that has a lower oxygen flow rate and a higher power substrate bias than a second part of the etch process. Etching the low dielectric constant film includes exposing the substrate to carbon tetrafluoride, oxygen, nitrogen, and argon.

Description

technical field [0001] Embodiments of the invention generally relate to methods for semiconductor processing. More specifically, embodiments of the present invention relate to methods for forming spacers with low dielectric constants. Background technique [0002] Ultra Large Scale Integration (ULSI) circuits typically include more than one million transistors on a semiconductor substrate that cooperate to perform various functions within the electronic device. The ULSI circuit may include complementary metal oxide semiconductor (CMOS) field effect transistors. [0003] A CMOS transistor includes a gate structure located between a source and a drain of a semiconductor substrate. The gate structure (stack) generally includes a gate formed on a gate dielectric material. The gate controls the flow of charged carriers under the gate dielectric in the channel region formed between the drain and source. Typically, spacers disposed adjacent to the gate stack form sidewalls on e...

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Problems solved by technology

However, high deposition temperatures require large thermal cycling of gate devices, which is incompatible with advanced device fabrication for 0.09 micron technology and beyond

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