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FEOL/MEOL metal resistor for high end CMOS

A technology of resistors and metals, applied in the field of complementary metal oxide semiconductors, can solve problems such as low parasitic capacitance

Inactive Publication Date: 2007-12-12
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] None of the above prior art resistors have all the advantages such as tight sheet resistance tolerance, high current density and low parasitic capacitance required by current semiconductor ICs

Method used

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  • FEOL/MEOL metal resistor for high end CMOS
  • FEOL/MEOL metal resistor for high end CMOS
  • FEOL/MEOL metal resistor for high end CMOS

Examples

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no. 1 example

[0043] First Embodiment: Reference is first made to the embodiment described in Figures 1A-1F. This embodiment initially provides the structure 10 shown in Figure 1A. Structure 10 includes a processed semiconductor substrate 12 including at least one trench isolation region 14 in semiconductor substrate 12 , and at least one FEOL device 16 on a surface of semiconductor substrate 12 . In this figure, at least one FEOL device 16 is a field effect transistor (FET) comprising a source / drain region 18, a silicide region 20 atop the source / drain region 18, a gate dielectric 22, A gate conductor 24 , an optional silicide region 20 ′ on gate conductor 24 , and at least one spacer 26 on at least a sidewall of gate conductor 24 . Although FETs are illustrated as FEOL devices, the present invention also contemplates other types of FEOL devices including, for example, bipolar transistors, BiCMOS devices, passive devices, and any other similar devices formed in the front end of processing...

no. 2 example

[0062] Second Embodiment: Referring to the structure 50 shown in FIG. 2A, which includes the semiconductor substrate 12, the trench isolation region 14, and the FEOL devices 16 and 16'. FEOL device 16 is a FET and FEOL device 16' is a bipolar device. For clarity, FEOL devices 16 and 16' are shown as a single box in the drawings of the present invention. The structure shown in FIG. 2A is formed using the techniques described in the first embodiment for FIG. 1A.

[0063] Next, a planarizing dielectric material 52 is formed, which may be, for example, an oxide of boron-doped silicate glass or another ILD-like material (see first embodiment above). The planarizing dielectric material 52 is formed by conventional deposition processes, and if desired, a planarizing process such as chemical mechanical polishing (CMP) or grinding may be used. The resulting structure comprising planarized dielectric material 52 is shown in FIG. 2B . Planarizing dielectric material 52 has a thickness...

no. 3 example

[0068] Third Embodiment: This embodiment differs from the previous embodiments in that the resistors comprise metal silicides, which are formed during silicidation of the FEOL device. A third embodiment of the invention begins by providing the structure 60 shown in Figure 3A. This structure includes at least one FEOL device 16 including at least one trench isolation region 14 on the surface of a semiconductor substrate 12 . The shown and illustrated FEOL device 16 is a FET that still does not contain any silicide regions. Although FET devices are shown, the third embodiment can work with other FEOL devices that include silicide regions.

[0069] Next, a suicide metal layer 62 is formed over the structure, providing the structure shown in FIG. 3B. The suicide metal 62 used in this embodiment of the invention includes any metal capable of reacting with silicon to form a metal suicide. Examples of such metals include, but are not limited to: Ti, Ta, W, Co, Ni, Pt, Pd and alloy...

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Abstract

A FEOL / MEOL metal resistor that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA / micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors as well as various methods of integrating such a metal resistor structure into a CMOS technology are provided.

Description

technical field [0001] This invention relates to metal resistors for use in semiconductor integrated circuits, and more particularly to methods of integrating metal resistors, such as refractory metal nitrides, into complementary metal oxide semiconductor (CMOS) technology. The invention also relates to semiconductor structures formed using the methods of the invention. Background technique [0002] In a semiconductor integrated circuit (IC), resistors may be used to control the resistance of other electronic components of the IC. It is well known to those skilled in the art that the resistance R of a resistor is proportional to the length L of the resistor and the reciprocal 1 / A of the cross-sectional area of ​​the resistor; L and A are measured in the direction of the current flow. The basic formula for the resistance of a resistor is: R is proportional to L / A, ie, Rα L / A, where R, L and A are defined as above. [0003] Prior art resistors typically consist of doped poly...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/20
CPCH01L28/24H01L29/7833H01L27/0629H01L27/02
Inventor 阿尼克·K.·秦塔金迪道格拉斯·D.·库尔伯格维德赫亚·拉马昌德兰罗伯特·M.·拉塞尔
Owner GLOBALFOUNDRIES INC
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