EEPROM erasing and writing high voltage conversion control cache suitable for low voltage data writing

Abstract

The present invention provides an EEPROM erasing high-voltage conversion control buffer applicable to low-voltage data writing. The buffer comprises a MaskBuf module, a DataBuf module and a data writing-in control logical module. The true value end and the complementary value end of a SRAM memory are respectively connected with an earthed NMOS pipe; SET and RESET signals are respectively used to control NMOS pipe gates and write data into the SRAM memory. When the turn threshold of the SRAM memory is in proximity of 1 / 2VDD, the data which is written in has properties including stability, reliability, etc. In the process of the internal EEPROM erasion, the buffer outputs high-voltage control signals following the lifting conversion of the output high voltage of the EEPROM charge pump, and a data writing control logic is realized with a transmission gate (low-voltage pipe) logic. So with simple circuits and compact structure, the buffer optimizes the chip area to the largest extent and realizes the aim of the present invention.

Description

technical field [0001] The invention relates to an EEPROM erasing and writing high-voltage conversion control buffer, in particular to an EEPROM erasing and writing high-voltage conversion control buffer suitable for low-voltage data writing. Background technique [0002] With the development of technology and the expansion of application fields, various systems have higher and higher requirements for chips to work under low voltage. EEPROM memory chips are widely used in many low-voltage application fields, so reducing the operating voltage of EEPROM memory chips has become a major problem that needs to be solved urgently, and the EEPROM erasing and writing high-voltage conversion control register ( Hereinafter referred to as buffer) is one of the key factors to realize the stable and reliable application of low-voltage EEPROM. [0003] The main function of the EEPROM buffer is: after the data to be written is written into the buffer storage area, in the process of erasing...

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Problems solved by technology

[0008] 2) When writing "1" in node 2, the current loop formed between Mn4, Mn2 and GND will inevitably form a voltage drop on the Mn4 tube, causing the node 2 to further decrease; therefore, when writing "1" in node 2, The voltage on node 2 is almost the same as the flipping voltage of SRAM memory 5, making it almost impossible to write a "1" state at node 2 under low voltage conditions

[0009] In order to solve the problem that the single-ended EEPROM register cannot write data correctly when the voltage is low, the solution is to reduce the Mn2 tube size as much as possible and increase the Mn1 tube size so that the SRAM memory 5 written from the node 2 The flipping threshold is reduced below 1 / 2Vdd; after the size of the Mn2 tube is reduced, the current on Mn4, Mn2 and GND is reduced when node 2 writes "1", and the driving capability of node 4 is increased at the same time, and the size of the Mn4 tube is increased (or the Mn4 tube is designed with a low-threshold high-voltage NMOS tube, but it has high requirements on the process, and there are disadvantages such as uncertain reliability and high process cost), which reduces the pressure drop on the Mn4 tube; according to the degree of adjustment, generally single-ended The minimum operating voltage of the written EEPROM buffer can be reduced to about 1.5V

[0010] However, the above solution still has relatively large defects, such as the feedback of the Mp1, Mp2, Mn1 and Mn2 transistors in the SRAM memory 5 is extremely asymmetrical, the flipping threshold is low, and it is very susceptible to the parasitic influence of layout layout and wiring capacitance. There is a problem that it is easy to be changed by the coupling between lines to change the correct writing state; at the same time, to make the data can be written correctly at low voltage, the size of the Mn3 tube must be adjusted to be small enough to reduce the flipping threshold of the SRAM memory 5 and the writing of the node 2" 1", and the size of the Mn4 tube must be large enough to reduce the voltage drop on the Mn4 tube when node 2 writes "1"; therefore, the layout area of ​​MaskBuf and DataBuf will be larger, which is not conducive to chip cost control

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