Novel 8-digit RISC microcontroller framework

Abstract

The present invention discloses a novel 8-bit RISC microcontroller framework, comprising a two-stage four-segment pipeline structure. The two-stage four-segment pipeline structure comprises an instruction processing device, a data readout device, a data operation device, a data writing device, a state machine and a clock generator. Due to the structure, clocks are not coupled crosswise; steady clocks can be generated for sure; the devices depend on and backup each other. The preprocessing and processing to data greatly improve the anti-interference ability of the structure, so as to realize high productivity.

Description

[0001] This application is a divisional application of an invention patent application whose filing date is August 31, 2005, the application number is 200510029281.4, and the invention name is "A Novel 8-bit RISC Microcontroller Architecture". technical field [0002] The invention belongs to the field of semiconductor integrated circuit design, and in particular relates to a microcontroller (MCU) system framework. Background technique [0003] In recent years, the reduced instruction set (RISC) architecture of microcontrollers has gained widespread popularity. Although there are different opinions on what characteristics a RISC processor should have, various RISC architectures share the following characteristics: (1) most instructions are single-cycle instructions to facilitate pipelining of the structure; (2) independent and simple loading and store instructions are two-cycle instructions; (3) instruction decoding is usually hardwired rather than micro-decoding to speed up...

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Problems solved by technology

[0004] These characteristics of RISC microcontrollers also bring some essential defects and deficiencies: (1) The instruction set cannot be expanded; (2) There are many pipeline segments and stages, which brings the complexity of data correlation criteria in pipeline segments , sometimes even affects the data throughput of the pipeline; (3) the data memory and the program memory are multiplexed, there is no special register file, or the special register file is not separated from the general register file, which affects the access speed of these registers and limits the (4) Design for Testability (DFT) is not adopted, and the manufacturing and production quality of the product cannot be guaranteed in the application; (5) The biggest problem that has not yet been solved is: for the two-stage four-stage pipeline structure, each The modules cannot back up and rely on each other, let alone preprocess and process the data, which seriously affects the anti-interference ability of the structure

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