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Shallow groove isolation layer of semiconductor element and manufacturing method thereof

A semiconductor and trench technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to achieve the effects of low high temperature shrinkage amplitude, low surface selectivity, and good hole filling ability

Active Publication Date: 2008-07-30
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this method can improve the surface selectivity of the silicon oxide layer formed by the traditional SACVD method, when the trench size is below 65 nm, or even 45 nm, the aforementioned problems such as tight seams or voids will still occur.

Method used

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  • Shallow groove isolation layer of semiconductor element and manufacturing method thereof
  • Shallow groove isolation layer of semiconductor element and manufacturing method thereof
  • Shallow groove isolation layer of semiconductor element and manufacturing method thereof

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Embodiment Construction

[0038] Please refer to the Figure 2 to Figure 6 , Figure 2 to Figure 6 It is a schematic cross-sectional view of the first embodiment of the shallow trench isolation layer structure and manufacturing process of the present invention. First, if figure 2 As shown, a semiconductor substrate 50, such as a silicon substrate, is provided. Next, a pad oxide layer 52 with a thickness of approximately 30 angstroms to 200 angstroms is formed on the semiconductor substrate 50 . The pad oxide layer 52 can be formed by chemical vapor deposition or thermal oxidation growth. Subsequently, a pad nitride layer 54 with a thickness of approximately 500 angstroms to 2000 angstroms is covered on the pad oxide layer 52 , and together with the pad oxide layer 52 as a shielding layer 56 .

[0039] Then if image 3As shown, an opening 58 is formed in the masking layer 56 by a photolithography process and an etching process, and then the exposed semiconductor substrate 50 is etched downward thr...

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PUM

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Abstract

The invention provides a method for filling silica layers in grooves. Firstly, a subbase comprising a plurality of grooves is provided; a reactant gas with a first O3 / TEOS flow ratio is provided for a first sedimentation process so that a first silica layer is formed on the surface of the subbase and in the grooves all sidedly. The reactant gas with a second O3 / TEOS flow ratio is provided for a second sedimentation process so that a second silica layer is formed on the surface of the subbase. In addition, the second O3TEOS flow ratio is less than the first O3 / TEOS flow ratio.

Description

technical field [0001] The invention relates to an insulating structure of a semiconductor material and a manufacturing method thereof, in particular to an insulating structure and a method of manufacturing a semiconductor material by utilizing multiple deposition steps. Background technique [0002] In semiconductor materials, silicon oxide materials or silicon nitride materials are often used to make insulating structures for isolating electrical components. Generally, the dielectric layer or insulating structure is made by localized oxidation isolation (LOCOS) or thin film deposition process, such as silane (SiH 4 ), tetraethoxysilane (tetra-ethyl-ortho-silicate, TEOS) and oxygen and other gases react with each other to form a thin film on the surface of the semiconductor material and make it have the function of blocking electricity. [0003] In the 0.18 micron process, the electrical isolation technology of the active area is mainly shallow trench isolation (STI), whic...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762H01L21/316H01L27/02
Inventor 许绍达陈能国蔡腾群
Owner UNITED MICROELECTRONICS CORP
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