Through hole etching method and through hole mask

Abstract

A through hole etching method includes the following steps of: providing a through hole etching floor; forming a patterned slushing compound layer on the through hole etching floor; exposing a part of the through hole etching floor by the patterned slushing compound layer; depositing an auxiliary mask layer which covers the patterned slushing compound layer and the part of the through hole etching floor exposed by the patterned slushing compound layer; etching the auxiliary mask layer so as to form a through hole mask which comprises an auxiliary mask; etching the through hole etching floor by the through hole mask so as to form the through hole; the through hole mask includes the slushing compound layer with a confirmed graph which exposes a part of the through hole etching floor; the auxiliary mask which covers the side wall of the slushing compound layer with a confirmed graph; the auxiliary mask is added based on the inherent through hole mask so as to reduce the graph size of the through hole mask under an inherent condition and be beneficial to forming a through hole with expanded size limitation by utilizing the mask.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a through hole etching method and a through hole mask. Background technique [0002] With the continuous shrinking of the critical dimension of semiconductor devices, in order to form a resist layer pattern with a smaller critical dimension in the photolithography process, only using a shorter-wavelength exposure light source can no longer meet the actual needs. In recent years, the industry generally reduces the size of the pattern by adding some kind of processing after the resist layer pattern is formed. Specifically, in order to obtain via holes with smaller sizes, it is necessary to reduce the size of the via holes formed on the resist layer. [0003] Usually, a melting process can be used to reduce the size of the via. The melting process is a process of forming a contact hole pattern on the resist layer and then heat-treating the semiconductor substra...

AI Technical Summary

Problems solved by technology

The Chinese patent with the announcement number "CN1036814C" published on December 24, 1997 and the Chinese patent with the announcement number "CN1744282" published on March 8, 2006 both provide a new mask design to form a semiconductor device. hole method, applying the method, or combining the method using the water-soluble resin with the method provided in the above-mentioned reference documents, all can obtain a smaller through-hole size under the inherent process conditions, but the obtained through-hole The size is limited by the limit process conditions of lithography or the material properties of the resist layer and auxiliary materials such as water-soluble resins. Lithography limit process conditions are limited; if a new mask design is used, supplemented with auxiliary masks such as water-soluble resins, in addition to being limited by lithography limit process conditions, it is also subject to water-soluble resins, etc. Limitations on material properties of auxiliary materials

Images