Field effect transistor having field plate electrodes

Abstract

A field effect transistor includes an active layer formed on a semiconductor substrate, source and drain electrodes formed apart from each other on the active layer, a gate electrode formed between the source and drain electrodes, a first interlayer film formed on the active layer, a first field plate (FP) electrode connected to the gate electrode and provided on the first interlayer film between the gate and drain electrodes, a second interlayer film formed on the first interlayer film, and a second FP electrode connected to the source electrode and provided on the second interlayer film between the first FP and drain electrodes. The field effect transistor is provided which exhibits a comparatively high gain factor at high frequencies.

Description

technical field [0001] The present invention relates to field effect transistors having field plate electrodes. Background technique [0002] In a high output power FET among field effect transistors (FET: Field effect transistor), since a high voltage is applied to the drain terminal, it is generally required to reduce the gate leakage current between the gate and the drain, or to increase the gate withstand voltage. Conventionally, as a technique to meet these requirements, it has been disclosed that an electric field control electrode is provided between the gate electrode and the drain electrode (for example, refer to Patent Document 1), and that the gate electrode is formed on the first interlayer insulating film toward the A field plate (FP) electrode structure (FP electrode structure) (for example, refer to Patent Document 2) extending the drain side into an eaves shape alleviates electric field concentration between the gate and the drain. [0003] In addition, the ...

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Problems solved by technology

The SFP electrode is connected to the source electrode, so the FP electrode connected to the gate electrode can only be separated by the thickness of the second interlayer insulating film, and the capacitance (Cgs) between the gate and source of the FET increases, The problem of the degradation of the high-frequency gain characteristic of FET

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