Preparation method for shallow trench isolation structure

Abstract

The invention provides a preparation method used for a shallow ditch separation structure, comprising the steps as follows: firstly, at least a channel is formed in a semiconductor substrate; subsequently, mixing process is carried out so as to transplant a nitrogen-contained mixing agent into the internal wall of the upper part of the channel and lead the consistency of the nitrogen-contained mixing agent on the upper part of the channel to be higher than that of the lower part of the channel; subsequently, a rotary coating dielectric layer which is filled in the channel and covers the surface of the semiconductor substrate is formed; subsequently, a thermal-oxidation process is carried out so as to form an silicon oxide which coves the internal wall of the channel. As the consistency of the nitrogen-contained mixing agent which can restrict the oxidation speed on the upper part of the channel is higher than that of the lower part of the channel, the thickness of the silicon oxide layer on the lower part of the channel is more than that of the upper part of the channel.

Description

technical field [0001] The invention relates to a preparation method of a shallow trench isolation structure, in particular to a preparation method of a shallow trench isolation structure without a silicon nitride liner and in which the silicon oxide layer on the inner wall of the channel has a structure of thin top and thick bottom. Background technique [0002] Conventional semiconductor processes generally use local oxidation of silicon (LOCOS) or shallow trench isolation (STI) to electrically isolate electronic components on a chip in order to avoid short circuits caused by electronic components interfering with each other. Since the field oxide layer formed by the local silicon oxidation method occupies a large area of ​​the chip and will be accompanied by the formation of a bird's beak phenomenon, the shallow trench isolation method is often used in advanced semiconductor processes to electrically isolate electronic components. [0003] Figure 1 to Figure 4 A method f...

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Problems solved by technology

However, the above-mentioned process cannot be applied to the preparation of flash memory due to the use of the silicon nitride liner 26 which is prone to form defects that can trap electrons.

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