Method for producing semiconductor chip, and field effect transistor and method for manufacturing same
A field-effect transistor and manufacturing method technology, which is applied in semiconductor/solid-state device manufacturing, transistors, semiconductor devices, etc., can solve the problems of difficult to change the thickness of silicon chips, high cost of SOI substrates, limited number of silicon chips, etc. The effect of low cost and large design freedom
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Embodiment approach 1
[0054] refer to Figure 1A-1F with Figure 2A-2E An example of a method of manufacturing a semiconductor chip will be described below. Figure 1A , 1C , 1E, 2A and 2C are top views. Figure 1B , 1D , 1F, 2B and 2D are respectively Figure 1A , 1C , Sectional views of 1E, 2A and 2C. In addition, the following diagrams are schematic diagrams. Actually, several hundred or more small pieces of semiconductor crystals can be produced from one wafer.
[0055] First, if Figure 1A with 1B As shown, three sacrificial layers 11 and three semiconductor crystal layers 12 are alternately stacked on a substrate 10 . These layers are formed by the CVD method.
[0056] As the material of the semiconductor crystal layer 12, for example, group IV semiconductors of Si, Ge, SiGe, and SiGeC, group III-V semiconductors of GaAs, GaP, GaAsP, GaSb, InP, InAs, and InAsP, group III semiconductors of ZnS, ZnSe, CdS, and CdSe II-VI semiconductor. The semiconductor crystal layer 12 may be a lay...
Embodiment approach 2
[0076] In Embodiment 2, an example of a method of manufacturing a semiconductor crystal chip having low-resistance regions at both ends will be described. Figure 4A-4F A part of the manufacturing process of Embodiment 2 is shown. Figure 4A , 4C and 4E are top views, Figure 4B , 4D and 4E are their cross-sectional views.
[0077] First, if Figure 4A with 4B As shown, on a substrate 10, a plurality of sacrificial layers 11 and a plurality of semiconductor crystal layers 12 are alternately stacked. Next, if Figure 4C with 4D As shown, a mask (resist pattern) 41 is formed on the semiconductor crystal layer 12, and impurities are doped at a high concentration. By this doping, a low-resistance region 12 a is formed on a part of the semiconductor crystal layer 12 . The doping amount of the low resistance region 12a is, for example, 1×10 18 cm -3 ~5×10 20 cm -3 About (preferably 5×10 19 cm -3 above). At this time, a plurality of low-resistance regions 12a having d...
Embodiment approach 3
[0081] In Embodiment 3, an example of a method of manufacturing a semiconductor crystal chip having an insulating layer formed on one main surface will be described. Figures 6A-6H A part of the manufacturing process of Embodiment 3 is shown. Figure 6A , 6C , 6E and 6G are top views, Figure 6B , 6D , 6F and 6H are their cross-sectional views.
[0082] First, if Figure 6A with 6B As shown, on the substrate 10 , the sacrificial layer 11 , the semiconductor crystal layer 12 and the insulating layer 61 are stacked repeatedly in this order. The insulating layer 61 is made of a material whose etching rate is slower than that of the sacrificial layer 11 like the semiconductor crystal layer 12 . As an example of the combination of the sacrificial layer 11, the semiconductor crystal layer 12, and the insulating layer 61, a combination of the sacrificial layer 11 made of silicon oxide, the semiconductor crystal layer 12 made of polysilicon, and the insulating layer 61 made of s...
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