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Dual lateral wall for flash memory

A dual, flash memory technology, applied in electrical components, electric solid state devices, circuits, etc., can solve the problems of difficult removal, poor data preservation characteristics, inability to meet the requirements of flash memory cell arrays and peripheral devices at the same time, and achieve higher breakdown voltage. , the effect of improving data retention capabilities

Inactive Publication Date: 2009-02-25
SEMICON MFG INT (SHANGHAI) CORP
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AI Technical Summary

Problems solved by technology

However, silicon nitride has a significant disadvantage that it is difficult to remove, so it is difficult to remove too much silicon nitride sidewall for the narrow sidewalls required by flash memory cell arrays
Although plasma-enhanced oxides or oxides / nitrides / oxides can be easily removed, their data retention characteristics are relatively poor and cannot meet the data storage requirements of flash memory cell arrays.
[0005] It can be seen that no matter whether a single silicon nitride, plasma-enhanced oxide or oxide / nitride / oxide is used as the sidewall in the prior art, it cannot meet the requirements of both the flash memory cell array and the peripheral device.

Method used

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  • Dual lateral wall for flash memory

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Embodiment Construction

[0035] The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0036] The present invention firstly provides a double sidewall applied to flash memory, the double sidewall includes a first ion-enhanced oxide layer, silicon nitride and a second plasma-enhanced oxide layer;

[0037] Wherein, the second plasma-enhanced oxide layer is removed when depositing the interlayer dielectric layer in the double sidewall of the flash memory cell array;

[0038] Applied in secondary arrays of flash memory peripherals, all layers are retained during the source / drain implantation of the peripherals, and the second plasma-enhanced oxide layer is removed during the deposition of the interlevel dielectric layer.

[0039] In one process flow, the second plasma-enhanced oxide layer is removed by wet etching for the dual sidewalls applied to the flash memory cell array.

[0040] In one process flow, for dual ...

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Abstract

The invention discloses a double side wall used for a flash memory. The double side wall comprises a first ion strengthened oxide layer, a silicon nitride and a second plasma strengthened oxide layer. When applied in the double side wall of a flash memory unit array, and when an interlayer dielectric medium layer is settled, the second plasma strengthened oxide layer is removed; when applied in the secondary array of a peripheral device of the flash memory, and when a source electrode and a leakage electrode of the peripheral device are planted, all layers are reserved. When the interlayer dielectric medium layer is settled, the second plasma strengthened oxide layer is removed. The invention further discloses a manufacture procedure method applied to the double side wall of the flash memory. When the source electrode and the leakage electrode of the peripheral device of the flash memory are planted, the side walls are thick, and when the interlayer dielectric medium is settled, the side walls are thin. Therefore, the breakdown voltage of the peripheral high voltage circuit is improved, and hollow holes are not generated because of the compact array when the flash array conducts the filling of the interlayer dielectric medium.

Description

technical field [0001] The present application relates to a manufacturing method of a flash memory device, and more specifically, to a manufacturing method applied to double sidewalls of a flash memory device. Background technique [0002] In flash memory (Flash) applications, flash memory cell arrays and peripheral devices of flash memory have different performance requirements. Generally, the flash cell array (Flash Cell Array) requires a relatively small gap to ensure that the interlayer dielectric void (Inter Layer Dielectric Void, ILD Void) in the contact hole (Contact) area can be avoided. Therefore, the flash memory cell array needs narrow sides. wall. The peripheral devices of the flash memory cell array require relatively large clearances to meet the requirements of high-voltage devices. For example, charge pumps and electrostatic charging (ESD) devices in the peripheral devices require high voltage. [0003] In the prior art, commonly used double sidewall materia...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/115H01L21/8247H10B69/00
Inventor 吴佳特李绍彬邬瑞彬
Owner SEMICON MFG INT (SHANGHAI) CORP