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Switching circuit arrangement

A technology of switching circuits and switching devices, which is applied in the direction of electronic switches, electrical components, and adjusting electrical variables, etc., which can solve problems such as spurious and voltage ringing, reduce energy loss, reduce switching loss, and optimize avalanche breakdown level Effect

Inactive Publication Date: 2009-06-10
KONINKLIJKE PHILIPS ELECTRONICS NV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] US 6819 149 B2 employs timing control to minimize voltage ringing of the switch node voltage of the half-bridge, this timing control results in spurious shoot-through, which creates additional losses in the switched circuit resulting in reduced voltage ringing;

Method used

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Embodiment Construction

[0045] Figure 1A Corresponding parts to FIG. 4D bear the same reference numerals.

[0046] In order to better understand the solution proposed according to the present invention, by way of example, in Figure 1A , Figure 1B with Figure 1C An in-depth look at synchronous buck converter operation is presented in . Figure 1A shows the circuit arrangement, Figure 1B with Figure 1C An operational diagram of such a synchronous buck converter 10 including a model of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET reference numeral 20 ) is shown.

[0047] Figure 1B The power waveform of is showing the loss mode LS of the synchronous buck converter 10 . High losses occur during switching transients, especially in the control field effect transistor 30 .

[0048] right Figure 1C The switch node voltage V x A more detailed observation of the leading edge transition LE, reveals that through the control field effect transistor 30 ( Figure 1C The presence of an ...

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Abstract

A switching circuit arrangement (100) comprises a field effect transistor (40) and circuitry (50, 52, 54, 60, 62) for biasing the gate voltage of the field effect transistor (40), in particular forcing the gate voltage of the field effect transistor (40) under a certain threshold, in particular under a certain positive threshold level. In embodiments, reverse recovery as well as gate bounce are simultaneously mitigated. In one embodiment, the biasing circuitry comprises a biasing diode (52) connected in series to the gate (G) of the field effect transistor (40) to bias the gate voltage of the field effect transistor (40), as well as a clamping field effect transistor unit (62) connected between the gate (G) of the field effect transistor (40) and the source (S) of the field effect transistor (40) to force the gate voltage of the field effect transistor (40) under a certain threshold, in particular under a certain positive threshold level.

Description

technical field [0001] The invention relates to switching circuit arrangements. Background technique [0002] For the need to improve high feedback control dynamics and reduce printed circuit board (PCB) space in low-voltage high-current applications such as voltage regulator modules (VRM) or point-of-load (PoL), high-frequency power conversion Essentially the most heartwarming solution. [0003] However, high switching frequency operation is detrimental to maintaining high converter efficiency, which is especially needed in these applications. Therefore, high efficiency is the main obstacle to increase switching frequency operation. This in turn significantly affects the design guidelines of converters, especially switching devices which have to maintain low conduction resistance and high switching performance. [0004] The most widely used converter topology in VRM and PoL applications is the synchronous buck. In such converters, two power switching loss mechanisms are...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K17/16H02M3/158
Inventor T·洛佩斯R·埃尔费里希
Owner KONINKLIJKE PHILIPS ELECTRONICS NV