Time clock generating circuit and design method

Abstract

The invention discloses a clock generating circuit and a design method thereof which comprises the following steps that an input module comprising a dispersion gate and an inverter is built, and a clock signal, which is received by the input module is transmitted into a buffer module and an output module according to an input signal; the buffer module comprising a plurality of inverters is built, and a buffer signal which is received by the buffer module, is generated according to the clock signal; the output module comprising a plurality of inverters is built, and clock signals, which are not mutually overlapped and are received by the output module, are buffered and output according to the clock signal and the buffer signal; a delay module comprising a transfer gate and a PMOS transistor is built, and a delay signal is generated by delaying the clock signal by the delay module, wherein, the output module, the buffer module and the delay module are connected in sequence, and the delay signal generated from the delay module is fed back to the input module as an input signal. Through adopting the clock generating circuit and the design method thereof, the performance of the clock generating circuit is improved and the chip space and the production cost of the chip are reduced.

Description

technical field [0001] The invention mainly relates to the field of integrated circuits, in particular to a clock generation circuit and a design method. Background technique [0002] In ∑-△ analog-to-digital converter (ADC, Analog-to-Digital Converter) circuits, a switched capacitor integrator circuit is commonly used. In order to realize this integrator, a clock generation circuit is an essential circuit module. In order for the switched capacitor integrator circuit to work normally and achieve high performance, it is necessary to generate a clock signal with two non-overlapping phases, that is, two such clock signals are mutually inverse signals, and the two clock signals will not be high at the same time. If the clock signal is not well designed and the two clock signals overlap each other, it will cause leakage in the integration process, thereby introducing unnecessary noise into the signal and affecting the performance of the switched capacitor integrator circuit. ...

AI Technical Summary

Problems solved by technology

However, these too many inverters composed of large-size CMOS transistors will occupy a large chip area, increase the manufacturing cost of the chip, and also increase the power consumption of the circuit, which is not conducive to the design and application of low-power chips.

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