Unlock instant, AI-driven research and patent intelligence for your innovation.

Take-and-measure wafer bonding method

A bonding method and wafer technology, applied in semiconductor/solid-state device testing/measurement, electrical components, semiconductor/solid-state device manufacturing, etc., to achieve the effect of maintaining cleanliness, reducing process time, and making extensive use of value

Inactive Publication Date: 2009-08-05
POWERTECH TECHNOLOGY
View PDF0 Cites 8 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] Another object of the present invention is to provide a new chip bonding method that is ready to be tested. The technical problem to be solved is to reduce the particle pollution caused by probing the electrode ends of the chip during the chip test, so as to maintain the chip. Cleanliness, which is more suitable for practical

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Take-and-measure wafer bonding method
  • Take-and-measure wafer bonding method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0034] In order to further explain the technical means and effects adopted by the present invention to achieve the intended purpose of the invention, the specific implementation method, Steps, features and effects thereof are described in detail below. For convenience of description, in the following embodiments, the same elements are denoted by the same numbers.

[0035] According to an embodiment of the present invention, a pick-and-measure wafer bonding method is disclosed. see figure 1 A schematic diagram of the working path of a grab-and-measure wafer bonding method is shown in . According to the wafer bonding method, at least one wafer 10 is firstly provided, and the active surface 12 of the wafer 10 has a plurality of electrode terminals 11 . The wafer 10 may be from a diced wafer. And a wafer bonding machine (or claiming die bonding machine) includes at least one pick-and-place suction nozzle 30, and plans a source area 40, a plurality of die-bonding regions 51, 52...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a wafer bonding method with the function of taking and measuring simultaneously, and is implemented in a wafer-sticking process after a wafer is cut; when the wafer is picked and placed, the function level thereof is synchronously tested. The pick-and-place suction nozzle which is used has a plurality of probes for detecting and touching the electrode end of the absorbed wafer; moreover, a corresponding movement path is selected according to the function lever of the wafer so as to move the pick-and-place suction nozzle to a corresponding type of wafer-sticking area, so the wafer which is absorbed by the pick-and-place suction nozzle can be placed to a wafer carrier in the corresponding wafer-sticking area. Therefore, in the wafer bonding process, wafer test and classification can be finished, the flow time can be reduced, and the wafer of good quality and the wafer of similar lever can be installed on the same wafer carrier so as to form a good package unit.

Description

technical field [0001] The invention relates to a manufacturing technology of a semiconductor device, a chip bonding process after cutting a semiconductor wafer, in particular to a chip bonding method which can be taken out and measured immediately. Background technique [0002] In the front-end process of semiconductors, it can be mainly divided into IC (integrated circuit) design, wafer fabrication (wafer fabrication, wafer fab for short), wafer test (wafer probe) and wafer cutting. After the integrated circuit chips are properly sorted, various packaging processes can be carried out. [0003] Wafer testing is to use testing machines and probe cards to test each die or chip on the wafer to ensure that the electrical characteristics and performance of the die are manufactured according to the design specifications. The detection head of the test machine is equipped with a hair-thin probe (probe), which is in contact with the electrode terminal (pad) on the die to test its ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/50H01L21/58H01L21/66
Inventor 方立志范文正林南君
Owner POWERTECH TECHNOLOGY