Silicon-on-insulator (SOI) circuit ESD global protecting structure

Abstract

The invention relates to the technical field of semiconductors and discloses a silicon-on-insulator (SOI) circuit ESD global protecting structure comprising the steps: a primary ESD protecting structure and a secondary ESD protecting structure protect an input end; an intelligent resistance ESD protecting structure, an output effusion pipe structure controlled by an RC circuit, and an output ESD protecting structure protect an output end / bi-directional end; a loop effusion pipe protecting structure controlled by the RC circuit and a serial intelligent resistance structure are arranged between a power supply loop and an earth loop, used for protecting the power supply end and the earth end together with a parallel diode structure and assist the input end and the output end / bi-directional end to effuse ESD current. By using the invention, the problems that the SOI chip output end / bi-directional end has poor ESD current effusion capability and a single loop effusion pipe has limit capability for effusing the ESD current are solved so as to enable the ESD protecting capability of an SOI integrated circuit to be completely improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a global protection structure for a silicon-on-insulator (SOI) circuit electrostatic discharge protection (ESD). Background technique [0002] With the development of the semiconductor industry, especially after entering the deep submicron scale, on the one hand, the breakdown voltage of the oxide layer will be greatly reduced; on the other hand, due to the characteristics of thin silicon film and poor heat dissipation of SOI technology, the leakage Terminal electrostatic discharge (ESD) protection capabilities have also become very poor. As a result, the ESD protection problem of the SOI circuit becomes very serious. [0003] In order to overcome this problem, the industry adopts SAB technical protection processing on the structure connected with the PAD. However, experiments have shown that although this method can effectively improve the ESD resistance of the circuit ...

AI Technical Summary

Problems solved by technology

But in the SOI circuit, due to the very poor anti-ESD ability of the output tube, adding the effusion tube structure according to the method is like a drop in the bucket, and it is difficult to make the circuit reach 2000V ESD immunity.

[0005] In addition, due to the very poor ESD resistance of SOI MOS transistors, when the input terminal uses a MOS transistor with a smaller gate width as the secondary protection structure according to the bulk silicon technology, the secondary protection structure itself is also better than the secondary protection structure in the bulk silicon technology. more easily damaged

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