Analog sampling switch and analog-to-digital converter

Abstract

The invention discloses an analog sampling switch and an analog-to-digital converter using the same. The analog sampling switch comprises a sampling switch circuit which comprises a sampling switch tube, and is used for controlling conduction state of the sampling switch tube; and a comparator circuit for comparing input signal level and output signal level of the sampling switch tube, and taking a higher level terminal as a source electrode of the sampling switch tube. The analog sampling switch and the analog-to-digital converter can track the source electrode of the switch tube, eliminate nonlinear relation between the switch conduction resistance and input signals, enhance linearity of the whole sampling switch, and meet high-speed and high-precision requirements of a sampling holding circuit.

Description

technical field [0001] The invention mainly relates to the field of analog integrated circuits, in particular to an analog sampling switch and an analog-to-digital converter. Background technique [0002] With the development of DSP (Digital Signal Processing, digital signal processing) technology and DSP processors, more and more analog signals need to be converted into digital signals for processing, which makes the interface between analog signals and digital signals-ADC (Analog -to-Digital Converter, analog-to-digital converter) put forward higher requirements. SHA (Sample and Hold Amplifiers, sample and hold circuit) is a crucial unit in the analog-to-digital converter, and its performance directly determines the performance of the entire system. With the increase of sampling clock frequency, the traditional MOS (metal oxide semiconductor, metal oxide semiconductor) sampling switch is limited by non-ideal effects, such as nonlinearity of on-resistance, charge injection...

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Problems solved by technology

[0004] The inventor found in the process of realizing the present invention that the prior art has at least the following disadvantages: these solutions do not consider the characteristics of the source tracking change of the switch tube, and in the actual PMOS transistor, the source always follows the input and output signals In the high potential of the NMOS transistor, the situation is just the opposite, so the design of the fixed source will inevitably produce nonlinear distortion

At the same time, the hold error caused by charge injection and clock feedthrough effects cannot be ignored

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