SRAM dual-position unit wiring method

Abstract

The invention discloses an SRAM dual-position unit wiring method which wires bit lines BL and BLb, and power lines Vss and Vdd along vertical direction by Metal 2, and wires a word line WL along horizontal direction by Metal 3, which not only reduces resistance on connection lines of bit lines BL and BLb, but also reduces coupling capacitance of bit lines BL and BLb and circumferential wired lines, so that performance characteristic of SRAM is improved. In addition, the bit lines BL and BLb are wired by Metal 2 so that metal wiring above SRAM has one more selection.

Description

technical field [0001] The invention relates to a semiconductor device wiring method, in particular to a SRAM double-bit cell wiring method, and belongs to the technical field of silicon semiconductor devices. Background technique [0002] Static Random Access Memory (SRAM) is a type of semiconductor memory that retains data as long as power is supplied. SRAM has the advantages of low power consumption, fast data access speed and compatibility with CMOS logic technology, and is widely used in various electronic devices. [0003] A basic SRAM cell consists of two cross-coupled inverters and two access transistors. A typical six-transistor SRAM (6T SRAM) cell circuit structure is as follows figure 1 shown. Among them, the CMOS inverter composed of M1 and M2 is cross-coupled with the CMOS inverter composed of M3 and M4 to latch a binary number, and M5 and M6 are access transistors, which are stored when the memory is read and written. The function of connecting or disconnec...

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Problems solved by technology

[0007] The object of the present invention is to provide a kind of SRAM double-bit cell wiring method, to solve the existing method when BL and BLb use Metal3 to carry out wiring, increase the resistance on the self-connecting line and increase the problem of the coupling capacitance with peripheral wiring

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