VME bus motor controller based on FPGA chip

A motor controller and controller technology, applied in the direction of electrical program control, program control in sequence/logic controller, bus network, etc., can solve the problems of high cost and complex structure, and achieve fast data communication capability, good motor The effect of the control effect

Active Publication Date: 2010-01-06
中科华士电气科技南京有限公司
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  • Abstract
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AI Technical Summary

Problems solved by technology

[0002] The control system based on the VME bus is widely used in high-power AC speed control systems such as steel and rail transit. This bus system has the advantages of openness and real-time performance, but the structure is complex and the cost is high.

Method used

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  • VME bus motor controller based on FPGA chip
  • VME bus motor controller based on FPGA chip
  • VME bus motor controller based on FPGA chip

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Embodiment Construction

[0019] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0020] figure 1 It is a hardware block diagram of the controller of the present invention. The hardware structure of this controller mainly includes VME backplane connector 1, voltage conversion chip: +5V to +3.3V power chip 2, +5V to +2.5V power chip 3, +3.3V to +1.2V power chip 4, and VME bus address signal driving circuit 5, VME bus data transmission control signal driving circuit 6, VME bus data signal driving circuit 7, FPGA chip 8, optical fiber signal driver 9, optical fiber transmitter 10 and optical fiber receiver 11, the control The mechanical specifications of the device are 12 on a standard 6U circuit board. Among them, the VME backplane connector 1 is three rows of 96-pin standard terminals, which are used to physically connect the controller with the P1 slot of the VME bus backplane, and at the same time connect the signal and p...

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Abstract

The invention discloses a motor controller which is developed by taking a programmable logical chip (FPGA) as a core and is based on a VME bus. The motor controller and a single-board computer meeting a VME standard can form a motor control system. A hardware structure of the controller mainly comprises a VME backboard socket connector 1, a voltage conversion chip converting +5V into +3.3V, a power supply chip 2 converting +5V into +2.5V, a power supply chip 3 converting +3.3V into +1.2V, a power supply chip 4, a VME bus address signal drive circuit 5, a VME bus data transmission control signal drive circuit 6, a VME bus data signal drive circuit 7, an FPGA chip 8, an optical fiber signal driver 9, an optical fiber transmitter 10 and an optical fiber receiver 11; the mechanical specification of the controller is a standard 6U circuit board 12. By combining a VME bus single-board computer, the invention can realize quick data communication capability and reach a favorable motor control effect. Moreover, because the FPGA has hardware programmable capability, the invention can program and modify a logical structure inside the FPGA under a condition that an external circuit is fixed, and has certain flexibility.

Description

technical field [0001] The invention relates to the field of motor controllers, in particular to a motor control system based on the VME bus standard. Background technique [0002] The control system based on VME bus is widely used in high-power AC speed control systems such as steel and rail transit. This bus system has the advantages of openness and real-time performance, but its structure is complicated and the cost is high. [0003] Field-programmable gate array (FPGA) chips have hardware programmable capabilities and can develop a variety of combinational logic and sequential logic. Due to their flexibility and cost-effectiveness, FPGAs are also being used in motor control systems. [0004] In the patent 200510083982.6, the invention of realizing data exchange with the VME bus controller through a digital signal processing (DSP) chip is introduced. The invention involves a chip including a complex programmable logic device (CPLD), a dual-port memory (RAM) and a digital...

Claims

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Application Information

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IPC IPC(8): G05B19/05H04L12/40
Inventor 王飞葛琼璇王晓新刘洪池韦榕李耀华
Owner 中科华士电气科技南京有限公司
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