Chip edge etching device and related chip planarization method

Abstract

A chip edge etching device and a related chip planarization method are disclosed. The chip edge etching device comprises a chip protection mask, and the chip protection mask covers partial surface of the chip. The chip thereon is defined with a centre area and a chip area surrounding the centre area. The chip protection mask comprises a centre shield area and at least one chip edge shield area. The centre shield area fully covers the centre area of the chip, while the chip shield area extends out from the margin of the centre shield area, partial chip edge area of the chip is covered, and the residual part of the chip edge area is exposed.

Description

technical field [0001] The invention relates to a crystal edge etching device and a related wafer flattening method, in particular to a wafer flattening method using the crystal edge etching device. Background technique [0002] In the process of manufacturing a semiconductor device, many materials such as polysilicon layers, metal interconnection layers, and low dielectric material layers are often used to form a desired semiconductor device or integrated circuit. However, generally speaking, the film layer deposited on the wafer often has the problem of uneven thickness or uneven surface level, which makes the surface of the integrated circuit present a steep topography with ups and downs, which increases the subsequent processing. Difficulties in pattern transfer process, chemical mechanical polishing (CMP) process or other film deposition processes. Therefore, after entering the deep submicron semiconductor process, most of the semiconductor industry will use the CMP pr...

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Problems solved by technology

On the other hand, edge defects near the edge of the wafer may also directly affect the subsequent etching process or other deposition processes. For example, when the film thickness at the crystal edge is deeper, the etching process usually produces more undesirable nodules. Phenomenon

[0005] In view of this, the known method of film layer production will cause the product wafer to be difficult to pass the wafer acceptance test (wafer acceptance test, WAT) and reduce the yield (yield), which still needs further improvement

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