Vertical double-diffused MOS transistor testing structure

Abstract

A vertical double-diffused MOS transistor testing structure belongs to the technical field of semiconductors and comprises a semiconductor substrate, an epitaxial layer, a source doping region, a drain doping region, a channel region, an interlayer dielectric layer, a metal layer which covers the upper surface of the semiconductor substrate and is used for leading out a source electrode and a drain electrode, as well as a back metal layer covering the bottom surface of the semiconductor substrate, wherein the parts of the channel region below the source doping region and the drain doping region are overlapped to form a combined channel; a electrode led out by the metal layer which covers the surface of the epitaxial layer and is used for leading the drain electrode is a drain electrode used for testing, and the electrode led out by the back metal layer covering the bottom surface of the semiconductor substrate is just the true drain electrode of the vertical diffused MOS transistor. Bytaking the drain electrode used for testing and the source electrode as output electrodes for testing, the testing structure effectively realizes monitoring on actual parameters of the vertical diffused MOS transistor, overcomes token difficulties after grinding, and unifies testing procedures, thus further lowering costs of maintenance and development and improving product testing and feedback efficiency.

Description

technical field [0001] The invention relates to a test structure of a transistor device, in particular to a test structure suitable for a vertical double-diffused MOS transistor, and belongs to the technical field of semiconductors. Background technique [0002] In semiconductor integrated circuits, the circuit based on double-diffused MOS transistors, referred to as DMOS, uses the difference in lateral diffusion speed of two impurity atoms to form a self-aligned sub-micron channel, which can achieve high operating frequency and speed. [0003] Compared with ordinary MOS transistors, DMOS has two main differences in structure: one is that P-type and N-type impurities are sequentially diffused through the same oxide layer window to form a very short channel; A lightly doped N - The drift region has a much lower doping concentration than the channel region. This region bears most of the added drain voltage, thereby weakening the short channel effect and increasing the drain...

AI Technical Summary

Problems solved by technology

[0007] There are two main technical problems to be solved in the present invention, one is to solve the relatively large error in the WAT characterization process of the vertical double-diffused MOS transistor; Problem with test sequence mismatch between test characterization and most semiconductor device tests performed prior to semiconductor substrate backgrinding

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