Bit line leakage current compensation circuit for sub-threshold memory cell array
A memory cell array and compensation circuit technology, applied in information storage, static memory, digital memory information, etc., can solve the problems that the performance is easily affected by process deviation, the bit line swing is small in the read cycle, and the area loss is large. Achieve the effects of simple timing control signal, enhanced off current, and reduced area consumption
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[0020] Reference figure 2 , A bit line leakage current compensation circuit of a sub-threshold memory cell array of the present invention consists of a first compensation transistor P1, a second compensation transistor P2, a first precharge balance transistor P3, a second precharge balance transistor P4, and a third precharge balance transistor. The charge balance transistor P5, the first shielded transmission gate T1, the second shielded transmission gate T2, and the first logic storage capacitor CAP1 and the second logic storage capacitor CAP2 are composed of the source terminal of the first compensation transistor P1 and the second compensation transistor P2. The source terminal is connected in parallel with the power supply voltage, the gate terminal of the first compensation transistor P1 is connected to the input terminal of the first shielded transmission gate T1 and serves as the bit line terminal of the memory cell array, and the gate terminal of the second compensation...
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