Semiconductor device with dual-mosaic structure and forming method thereof

Abstract

The invention discloses a method for forming a semiconductor device with a dual-mosaic structure, which comprises the following steps of: providing a substrate; forming a first dielectric layer on the substrate; forming a through hole pattern on the first dielectric layer; forming an opening of a through hole; detecting the remaining thickness of the first dielectric layer which remains at the bottom of the opening of the through hole; forming a second dielectric layer on the first dielectric layer and in the opening of the through hole; forming a trench pattern on second dielectric layer; forming a trench; removing the second dielectric layer; adjusting process conditions of the third etching according to the remaining thickness; performing the third etching to remove the first dielectric layer which remains at the bottom of the opening of the through hole; and forming the dual-mosaic structure. The invention also discloses the semiconductor device with the dual-mosaic structure. The semiconductor device with the dual-mosaic structure and the forming method thereof of the invention form high-quality dual-mosaic structure below a stop layer without etching and effectively reduce k value of the dual-mosaic structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device with a double damascene structure and a forming method thereof. Background technique [0002] As the production of integrated circuits develops towards ultra-large-scale integrated circuits (ULSI), the internal circuit density is getting larger and larger, and the number of components contained is increasing, making the surface of the wafer unable to provide enough area to make the required interconnection ( Interconnect). Therefore, in order to meet the increased demand for interconnection lines after component shrinkage, the design of multilayer metal interconnection lines with more than two layers has become a method that must be adopted in VLSI technology. Among them, after entering the 0.18 micron process technology, the dual damascene structure of copper and low dielectric constant (low k value, low dielectric constant) dielectric...

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Problems solved by technology

However, this method cannot solve the problem that the above-mentioned existing dual damascene structure has a high k value and cannot meet the requirements of 45nm and below process nodes.

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